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author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-16 16:36:21 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-16 16:36:21 -0800 |
commit | 56adbaffd0a0fab320a64097cd6aa6e74473f840 (patch) | |
tree | 56fddd236c8210a66b91945b2a0ed775fcc667d7 /doc | |
parent | d7d857a1896005df53956565644b138a76a1f0ec (diff) | |
download | openocd+libswd-56adbaffd0a0fab320a64097cd6aa6e74473f840.tar.gz openocd+libswd-56adbaffd0a0fab320a64097cd6aa6e74473f840.tar.bz2 openocd+libswd-56adbaffd0a0fab320a64097cd6aa6e74473f840.tar.xz openocd+libswd-56adbaffd0a0fab320a64097cd6aa6e74473f840.zip |
ARMv7A: use standard disassembler
We no longer need v7A-specific code for this.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/openocd.texi | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 092de7d3..2767d787 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5535,10 +5535,17 @@ that is not currently supported in OpenOCD.) Disassembles @var{count} instructions starting at @var{address}. If @var{count} is not specified, a single instruction is disassembled. If @option{thumb} is specified, or the low bit of the address is set, -Thumb (16-bit) instructions are used; +Thumb2 (mixed 16/32-bit) instructions are used; else ARM (32-bit) instructions are used. (Processors may also support the Jazelle state, but those instructions are not currently understood by OpenOCD.) + +Note that all Thumb instructions are Thumb2 instructions, +so older processors (without Thumb2 support) will still +see correct disassembly of Thumb code. +Also, ThumbEE opcodes are the same as Thumb2, +with a handful of exceptions. +ThumbEE disassembly currently has no explicit support. @end deffn @deffn Command {arm reg} @@ -5941,23 +5948,6 @@ Displays the number of extra tck for mem-ap memory bus access [0-255]. If @var{value} is defined, first assigns that. @end deffn -@subsection ARMv7-A specific commands -@cindex ARMv7-A - -@deffn Command {armv7a disassemble} address [count [@option{thumb}]] -@cindex disassemble -Disassembles @var{count} instructions starting at @var{address}. -If @var{count} is not specified, a single instruction is disassembled. -If @option{thumb} is specified, or the low bit of the address is set, -Thumb2 (mixed 16/32-bit) instructions are used; -else ARM (32-bit) instructions are used. -With a handful of exceptions, ThumbEE instructions are the same as Thumb2; -ThumbEE disassembly currently has no explicit support. -(Processors may also support the Jazelle state, but -those instructions are not currently understood by OpenOCD.) -@end deffn - - @subsection Cortex-M3 specific commands @cindex Cortex-M3 |