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authorSpencer Oliver <ntfreak@users.sourceforge.net>2010-03-16 12:48:53 +0000
committerSpencer Oliver <ntfreak@users.sourceforge.net>2010-03-17 09:01:45 +0000
commit79ca05b106ef92915c4e9288cbf34d5db1cf4cd2 (patch)
treec2a64462af3ec19f11a7748c62c20700db23bf9e /doc
parent051e2c99ab8111f6bffdb412b40ceef333530ae6 (diff)
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MIPS: remove ejtag_srst variant
The mips_m4k_assert_reset has now been restructured so the variant ejtag_srst is not required anymore. The ejtag software reset will be used if the target does not have srst connected. Remove ejtag_srst from docs. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi8
1 files changed, 0 insertions, 8 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index e1bb2b77..780cd4d7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3453,14 +3453,6 @@ be detected and the normal reset behaviour used.
@item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926
@item @code{mips_m4k} -- a MIPS core. This supports one variant:
-@itemize @minus
-@item @code{ejtag_srst} ... Use this when debugging targets that do not
-provide a functional SRST line on the EJTAG connector. This causes
-OpenOCD to instead use an EJTAG software reset command to reset the
-processor.
-You still need to enable @option{srst} on the @command{reset_config}
-command to enable OpenOCD hardware reset functionality.
-@end itemize
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
There are several variants defined: