diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-27 18:50:26 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-27 18:50:26 -0800 |
| commit | e0cb27df6bc595650ca6ce205803d3aa3218e262 (patch) | |
| tree | 62a99e2b725a3c90b0e78129721579c818f3db5c /src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script | |
| parent | 4e56a2303b3f68bb647d8bb640a830f7f21ea231 (diff) | |
| download | openocd+libswd-e0cb27df6bc595650ca6ce205803d3aa3218e262.tar.gz openocd+libswd-e0cb27df6bc595650ca6ce205803d3aa3218e262.tar.bz2 openocd+libswd-e0cb27df6bc595650ca6ce205803d3aa3218e262.tar.xz openocd+libswd-e0cb27df6bc595650ca6ce205803d3aa3218e262.zip | |
Cortex-A8: support "reset-assert" event
Use the new "reset-assert" event; else SRST; else fail.
Tested on an OMAP3, using the event.
NOTE: still doesn't handle "reset halt". For some reason
neither VCR nor PRCR seemed effective; they held the value
that was written, but VCR didn't trigger debug entry when
the reset vector fired (maybe the vector needs configuring?)
and PRCR refused to hold the chip in reset until deassert()
could force the core into debug state.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script')
0 files changed, 0 insertions, 0 deletions