- str9x flash support (Thanks to Spencer Oliver)

- str75x flash support (Thanks to Spencer Oliver)
- correct reporting of T-Bit in CPSR (Thanks to John Hartman for reporting this)
- core-state (ARM/Thumb) can be switched by modifying CPSR
- fixed bug in gdb_server register handling
- register values > 32-bit should now be supported
- several minor fixes and enhancements



git-svn-id: svn://svn.berlios.de/openocd/trunk@100 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 85 insertions, 0 deletions

diff --git a/src/flash/str9x.h b/src/flash/str9x.h
new file mode 100644
index 00000000..0cd1f196
--- /dev/null
+++ b/src/flash/str9x.h
@@ -0,0 +1,85 @@
+/***************************************************************************
+ *   Copyright (C) 2005 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifndef STR9X_H
+#define STR9X_H
+
+#include "flash.h"
+#include "target.h"
+
+typedef struct str9x_flash_bank_s
+{
+	struct target_s *target;
+	u32 *sector_bits;
+	working_area_t *write_algorithm;
+} str9x_flash_bank_t;
+
+enum str9x_status_codes
+{
+	STR9X_CMD_SUCCESS = 0,
+	STR9X_INVALID_COMMAND = 1,
+	STR9X_SRC_ADDR_ERROR = 2,
+	STR9X_DST_ADDR_ERROR = 3,
+	STR9X_SRC_ADDR_NOT_MAPPED = 4,
+	STR9X_DST_ADDR_NOT_MAPPED = 5,
+	STR9X_COUNT_ERROR = 6,
+	STR9X_INVALID_SECTOR = 7,
+	STR9X_SECTOR_NOT_BLANK = 8,
+	STR9X_SECTOR_NOT_PREPARED = 9,
+	STR9X_COMPARE_ERROR = 10,
+	STR9X_BUSY = 11
+};
+
+/* FMI sectors */
+
+#define FMI_BANK_0	(0x5400000C << 2)			/* FMI Bank 0 */
+#define FMI_BANK_1	(0x54000010 << 2)			/* FMI Bank 1 */
+
+#define FMI_B0S0	(0x00000000 + FMI_BANK_0)	/* Bank 0 sector 0 */
+#define FMI_B0S1	(0x00010000 + FMI_BANK_0)	/* Bank 0 sector 1 */
+#define FMI_B0S2	(0x00020000 + FMI_BANK_0)	/* Bank 0 sector 2 */
+#define FMI_B0S3	(0x00030000 + FMI_BANK_0)	/* Bank 0 sector 3 */
+#define FMI_B0S4	(0x00040000 + FMI_BANK_0)	/* Bank 0 sector 4 */
+#define FMI_B0S5	(0x00050000 + FMI_BANK_0)	/* Bank 0 sector 5 */
+#define FMI_B0S6	(0x00060000 + FMI_BANK_0)	/* Bank 0 sector 6 */
+#define FMI_B0S7	(0x00070000 + FMI_BANK_0)	/* Bank 0 sector 7 */
+
+#define FMI_B1S0	(0x00000000 + FMI_BANK_1)	/* Bank 1 sector 0 */
+#define FMI_B1S1	(0x00002000 + FMI_BANK_1)	/* Bank 1 sector 1 */
+#define FMI_B1S2	(0x00004000 + FMI_BANK_1)	/* Bank 1 sector 2 */
+#define FMI_B1S3	(0x00006000 + FMI_BANK_1)	/* Bank 1 sector 3 */
+
+/*  Flash registers */
+
+#define FLASH_BBSR		0x54000000		/* Boot Bank Size Register                */
+#define FLASH_NBBSR		0x54000004		/* Non-Boot Bank Size Register            */
+#define FLASH_BBADR		0x5400000C		/* Boot Bank Base Address Register        */
+#define FLASH_NBBADR	0x54000010		/* Non-Boot Bank Base Address Register    */
+#define FLASH_CR		0x54000018		/* Control Register                       */
+#define FLASH_SR		0x5400001C		/* Status Register                        */
+#define FLASH_BCE5ADDR	0x54000020		/* BC Fifth Entry Target Address Register */
+
+typedef struct str9x_mem_layout_s {
+	u32 sector_start;
+	u32 sector_size;
+	u32 sector_bit;
+} str9x_mem_layout_t;
+
+#endif /* STR9X_H */
+