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author | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2006-08-31 12:41:49 +0000 |
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committer | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2006-08-31 12:41:49 +0000 |
commit | 3acb107b9ae4e3d38d3fcfd29b455ebcfb444696 (patch) | |
tree | b44896670fc255dad7c80d20321c3e1e0252f446 /src/flash | |
parent | da9eedc0f2c338b8ad136a4436a7781edc4a8884 (diff) | |
download | openocd+libswd-3acb107b9ae4e3d38d3fcfd29b455ebcfb444696.tar.gz openocd+libswd-3acb107b9ae4e3d38d3fcfd29b455ebcfb444696.tar.bz2 openocd+libswd-3acb107b9ae4e3d38d3fcfd29b455ebcfb444696.tar.xz openocd+libswd-3acb107b9ae4e3d38d3fcfd29b455ebcfb444696.zip |
- endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts
- added access to ARM920T vector catch register (via generic register mechanism)
- don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache
- read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands)
- memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes)
- made in_handler independent from in field (makes the handler more flexible)
- added timeout to ft2232 when using D2XX library
- fixed STR7x protection bit handling on second bank (thanks to Bernard)
- added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen)
- fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen)
git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/flash')
-rw-r--r-- | src/flash/at91sam7.c | 13 | ||||
-rw-r--r-- | src/flash/at91sam7.h | 2 | ||||
-rw-r--r-- | src/flash/str7x.c | 4 |
3 files changed, 11 insertions, 8 deletions
diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c index 59ed2aa0..dd8bdeb5 100644 --- a/src/flash/at91sam7.c +++ b/src/flash/at91sam7.c @@ -133,9 +133,10 @@ u32 at91sam7_get_flash_status(flash_bank_t *bank) { at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; target_t *target = at91sam7_info->target; - long fsr; + u32 fsr; target->type->read_memory(target, MC_FSR, 4, 1, (u8 *)&fsr); + fsr = target_buffer_get_u32(target, (u8 *)&fsr); return fsr; } @@ -206,7 +207,7 @@ void at91sam7_read_clock_info(flash_bank_t *bank) /* Setup the timimg registers for nvbits or normal flash */ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode) { - u32 fmcn, fmr; + u32 fmr, fmcn = 0, fws = 0; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; target_t *target = at91sam7_info->target; @@ -220,12 +221,14 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode) fmcn = (at91sam7_info->mck_freq/666666ul)+1; /* Only allow fmcn=0 if clock period is > 30 us. */ - if (at91sam7_info->mck_freq <= 33333) + if (at91sam7_info->mck_freq <= 33333333ul) fmcn = 0; + else + fws = 1; DEBUG("fmcn: %i", fmcn); - fmr = fmcn<<16; - target->type->write_memory(target, MC_FSR, 4, 1, (u8 *)&fmr); + fmr = fmcn << 16 | fws << 8; + target->type->write_memory(target, MC_FMR, 4, 1, (u8 *)&fmr); } at91sam7_info->flashmode = mode; } diff --git a/src/flash/at91sam7.h b/src/flash/at91sam7.h index c65600eb..e2412f8c 100644 --- a/src/flash/at91sam7.h +++ b/src/flash/at91sam7.h @@ -48,7 +48,7 @@ typedef struct at91sam7_flash_bank_s u8 num_erase_regions; u32 *erase_region_info; - /* nv memory bits */ + /* nv memory bits */ u16 num_lockbits; u16 lockbits; u16 num_nvmbits; diff --git a/src/flash/str7x.c b/src/flash/str7x.c index b7081208..2e04f6b1 100644 --- a/src/flash/str7x.c +++ b/src/flash/str7x.c @@ -44,8 +44,8 @@ str7x_mem_layout_t mem_layout[] = { {0x00010000, 0x10000, 0x01}, {0x00020000, 0x10000, 0x01}, {0x00030000, 0x10000, 0x01}, - {0x000C0000, 0x02000, 0x10}, - {0x000C2000, 0x02000, 0x10}, + {0x000C0000, 0x02000, 0x100}, + {0x000C2000, 0x02000, 0x100}, {0,0}, }; |