- Fixes '<<' whitespace

- Replace ')\(<<\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\(<<\)(' with '\1 \2 ('.
- Replace '\(\w\)\(<<\)\(\w\)' with '\1 \2 \3'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2370 b42882b7-edfa-0310-969c-e2dbd0fdcd60

15 files changed, 104 insertions, 104 deletions

diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index 55afb6bf..27779a39 100644
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -280,7 +280,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
 	at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 	target_t *target = bank->target;
 
-	fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; 
+	fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd; 
 	target_write_u32(target, MC_FCR[bank->bank_number], fcr);
 	LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
 
diff --git a/src/flash/cfi.c b/src/flash/cfi.c
index 774424e0..4cd5f4dc 100644
--- a/src/flash/cfi.c
+++ b/src/flash/cfi.c
@@ -2266,7 +2266,7 @@ static int cfi_probe(struct flash_bank_s *bank)
 			(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
 			(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
 
-		cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
+		cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
 		cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
 		cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
 		cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
diff --git a/src/flash/non_cfi.c b/src/flash/non_cfi.c
index 3e86e0da..47313672 100644
--- a/src/flash/non_cfi.c
+++ b/src/flash/non_cfi.c
@@ -29,7 +29,7 @@
 
 #define KB 1024
 #define MB (1024*1024)
-#define ERASE_REGION(num, size) (((size/256)<<16)|(num-1))
+#define ERASE_REGION(num, size) (((size/256) << 16)|(num-1))
 
 /* non-CFI compatible flashes */
 non_cfi_t non_cfi_flashes[] = {
diff --git a/src/flash/ocl.c b/src/flash/ocl.c
index 9997bc0b..a83f5ea8 100644
--- a/src/flash/ocl.c
+++ b/src/flash/ocl.c
@@ -208,13 +208,13 @@ static int ocl_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset
 					*dcc_bufptr &= *(buffer++) | 0xffffff00;
 					break;
 				case 1:
-					*dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
+					*dcc_bufptr &= ((*(buffer++)) << 8) | 0xffff00ff;
 					break;
 				case 2:
-					*dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
+					*dcc_bufptr &= ((*(buffer++)) << 16) | 0xff00ffff;
 					break;
 				case 3:
-					*dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
+					*dcc_bufptr &= ((*(buffer++)) << 24) | 0x00ffffff;
 					chksum ^= *(dcc_bufptr++);
 					*dcc_bufptr = 0xffffffff;
 					byteofs = 0;
diff --git a/src/flash/ocl/at91sam7x/main.c b/src/flash/ocl/at91sam7x/main.c
index 6ecbf35a..b49a5b89 100644
--- a/src/flash/ocl/at91sam7x/main.c
+++ b/src/flash/ocl/at91sam7x/main.c
@@ -88,7 +88,7 @@ int main (void)
 				dcc_wr(0x100000); /* base */
 				dcc_wr(flash_page_count*flash_page_size); /* size */
 				dcc_wr(1); /* num_sectors */
-				dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
+				dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
 				break;
 			case OCL_ERASE_ALL:
 				dcc_wr(OCL_CMD_DONE|flash_erase_all());
diff --git a/src/flash/ocl/at91sam7x/samflash.c b/src/flash/ocl/at91sam7x/samflash.c
index b5255191..893b579f 100644
--- a/src/flash/ocl/at91sam7x/samflash.c
+++ b/src/flash/ocl/at91sam7x/samflash.c
@@ -100,7 +100,7 @@ int flash_page_program(uint32 *data, int page_num)
 	}
 
 	/* page number and page write command to FCR */
-	outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
+	outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
 
 	/* wait until it's done */
 	while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
@@ -136,7 +136,7 @@ int flash_erase_plane(int efc_ofs)
 			/* wait until FLASH is ready, just for sure */
 			while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
 
-			outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
+			outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
 
 			/* wait until it's done */
 			while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
diff --git a/src/flash/pic32mx.c b/src/flash/pic32mx.c
index dd24a7dc..7009995a 100644
--- a/src/flash/pic32mx.c
+++ b/src/flash/pic32mx.c
@@ -194,11 +194,11 @@ static int pic32mx_protect_check(struct flash_bank_s *bank)
 	}
 
 	target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
-	if ((devcfg0 & (1<<28)) == 0) /* code protect bit */
+	if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
 		num_pages = 0xffff;  /* All pages protected */
 	else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
 	{
-		if (devcfg0 & (1<<24))
+		if (devcfg0 & (1 << 24))
 			num_pages = 0;       /* All pages unprotected */
 		else
 			num_pages = 0xffff;  /* All pages protected */
diff --git a/src/flash/pic32mx.h b/src/flash/pic32mx.h
index 49c8f5fa..49a9bb40 100644
--- a/src/flash/pic32mx.h
+++ b/src/flash/pic32mx.h
@@ -80,11 +80,11 @@ typedef struct pic32mx_flash_bank_s
 #define PIC32MX_NVMCONCLR	0xBF80F404
 #define PIC32MX_NVMCONSET	0xBF80F408
 #define PIC32MX_NVMCONINV	0xBF80F40C
-#define NVMCON_NVMWR		(1<<15)
-#define NVMCON_NVMWREN		(1<<14)
-#define NVMCON_NVMERR		(1<<13)
-#define NVMCON_LVDERR		(1<<12)
-#define NVMCON_LVDSTAT		(1<<11)
+#define NVMCON_NVMWR		(1 << 15)
+#define NVMCON_NVMWREN		(1 << 14)
+#define NVMCON_NVMERR		(1 << 13)
+#define NVMCON_LVDERR		(1 << 12)
+#define NVMCON_LVDSTAT		(1 << 11)
 #define NVMCON_OP_PFM_ERASE		0x5
 #define NVMCON_OP_PAGE_ERASE	0x4
 #define NVMCON_OP_ROW_PROG		0x3
diff --git a/src/flash/s3c24xx_regs_nand.h b/src/flash/s3c24xx_regs_nand.h
index 31d9a856..c8cbe789 100644
--- a/src/flash/s3c24xx_regs_nand.h
+++ b/src/flash/s3c24xx_regs_nand.h
@@ -59,63 +59,63 @@
 #define S3C2412_NFMECC1		S3C2410_NFREG(0x38)
 #define S3C2412_NFSECC		S3C2410_NFREG(0x3C)
 
-#define S3C2410_NFCONF_EN          (1<<15)
-#define S3C2410_NFCONF_512BYTE     (1<<14)
-#define S3C2410_NFCONF_4STEP       (1<<13)
-#define S3C2410_NFCONF_INITECC     (1<<12)
-#define S3C2410_NFCONF_nFCE        (1<<11)
-#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY        (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8	(0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16	(1<<0)
-#define S3C2440_NFCONF_ADVFLASH		(1<<3)
-#define S3C2440_NFCONF_TACLS(x)		((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x)	((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x)	((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT	(1<<13)
-#define S3C2440_NFCONT_SOFTLOCK		(1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN	(1<<10)
-#define S3C2440_NFCONT_RNBINT_EN	(1<<9)
-#define S3C2440_NFCONT_RN_FALLING	(1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK	(1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK	(1<<5)
-#define S3C2440_NFCONT_INITECC		(1<<4)
-#define S3C2440_NFCONT_nFCE			(1<<1)
-#define S3C2440_NFCONT_ENABLE		(1<<0)
-
-#define S3C2440_NFSTAT_READY		(1<<0)
-#define S3C2440_NFSTAT_nCE			(1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE	(1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS	(1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT		(1<<31)
-#define S3C2412_NFCONF_ECCCLKCON	(1<<30)
-#define S3C2412_NFCONF_ECC_MLC		(1<<24)
-#define S3C2412_NFCONF_TACLS_MASK	(7<<12)	/* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR	(1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT	(1<<17)
-#define S3C2412_NFCONT_SOFTLOCK		(1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT	(1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT	(1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK	(1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC	(1<<5)
-#define S3C2412_NFCONT_nFCE1		(1<<2)
-#define S3C2412_NFCONT_nFCE0		(1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE	(1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE	(1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS	(1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE	(1<<4)
-#define S3C2412_NFSTAT_nFCE1		(1<<3)
-#define S3C2412_NFSTAT_nFCE0		(1<<2)
-#define S3C2412_NFSTAT_Res1			(1<<1)
-#define S3C2412_NFSTAT_READY		(1<<0)
+#define S3C2410_NFCONF_EN          (1 << 15)
+#define S3C2410_NFCONF_512BYTE     (1 << 14)
+#define S3C2410_NFCONF_4STEP       (1 << 13)
+#define S3C2410_NFCONF_INITECC     (1 << 12)
+#define S3C2410_NFCONF_nFCE        (1 << 11)
+#define S3C2410_NFCONF_TACLS(x)    ((x) << 8)
+#define S3C2410_NFCONF_TWRPH0(x)   ((x) << 4)
+#define S3C2410_NFCONF_TWRPH1(x)   ((x) << 0)
+
+#define S3C2410_NFSTAT_BUSY        (1 << 0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8	(0 << 0)
+#define S3C2440_NFCONF_BUSWIDTH_16	(1 << 0)
+#define S3C2440_NFCONF_ADVFLASH		(1 << 3)
+#define S3C2440_NFCONF_TACLS(x)		((x) << 12)
+#define S3C2440_NFCONF_TWRPH0(x)	((x) << 8)
+#define S3C2440_NFCONF_TWRPH1(x)	((x) << 4)
+
+#define S3C2440_NFCONT_LOCKTIGHT	(1 << 13)
+#define S3C2440_NFCONT_SOFTLOCK		(1 << 12)
+#define S3C2440_NFCONT_ILLEGALACC_EN	(1 << 10)
+#define S3C2440_NFCONT_RNBINT_EN	(1 << 9)
+#define S3C2440_NFCONT_RN_FALLING	(1 << 8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK	(1 << 6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK	(1 << 5)
+#define S3C2440_NFCONT_INITECC		(1 << 4)
+#define S3C2440_NFCONT_nFCE			(1 << 1)
+#define S3C2440_NFCONT_ENABLE		(1 << 0)
+
+#define S3C2440_NFSTAT_READY		(1 << 0)
+#define S3C2440_NFSTAT_nCE			(1 << 1)
+#define S3C2440_NFSTAT_RnB_CHANGE	(1 << 2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS	(1 << 3)
+
+#define S3C2412_NFCONF_NANDBOOT		(1 << 31)
+#define S3C2412_NFCONF_ECCCLKCON	(1 << 30)
+#define S3C2412_NFCONF_ECC_MLC		(1 << 24)
+#define S3C2412_NFCONF_TACLS_MASK	(7 << 12)	/* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR	(1 << 18)
+#define S3C2412_NFCONT_LOCKTIGHT	(1 << 17)
+#define S3C2412_NFCONT_SOFTLOCK		(1 << 16)
+#define S3C2412_NFCONT_ECC4_ENCINT	(1 << 13)
+#define S3C2412_NFCONT_ECC4_DECINT	(1 << 12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK	(1 << 7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC	(1 << 5)
+#define S3C2412_NFCONT_nFCE1		(1 << 2)
+#define S3C2412_NFCONT_nFCE0		(1 << 1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE	(1 << 7)
+#define S3C2412_NFSTAT_ECC_DECDONE	(1 << 6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS	(1 << 5)
+#define S3C2412_NFSTAT_RnB_CHANGE	(1 << 4)
+#define S3C2412_NFSTAT_nFCE1		(1 << 3)
+#define S3C2412_NFSTAT_nFCE0		(1 << 2)
+#define S3C2412_NFSTAT_Res1			(1 << 1)
+#define S3C2412_NFSTAT_READY		(1 << 0)
 
 #define S3C2412_NFECCERR_SERRDATA(x)	(((x) >> 21) & 0xf)
 #define S3C2412_NFECCERR_SERRBIT(x)		(((x) >> 18) & 0x7)
diff --git a/src/flash/stellaris.c b/src/flash/stellaris.c
index 8f5f03a0..09d7f0dd 100644
--- a/src/flash/stellaris.c
+++ b/src/flash/stellaris.c
@@ -665,9 +665,9 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int
 	for (lockregion = first; lockregion <= last; lockregion++)
 	{
 		if (set)
-			fmppe &= ~(1<<lockregion);
+			fmppe &= ~(1 << lockregion);
 		else
-			fmppe |= (1<<lockregion);
+			fmppe |= (1 << lockregion);
 	}
 
 	/* Clear and disable flash programming interrupts */
diff --git a/src/flash/stellaris.h b/src/flash/stellaris.h
index f2d37605..18fd3f24 100644
--- a/src/flash/stellaris.h
+++ b/src/flash/stellaris.h
@@ -82,11 +82,11 @@ typedef struct stellaris_flash_bank_s
 #define PMASK	2
 
 /* Flash Controller Command bits */
-#define FMC_WRKEY	(0xA442<<16)
-#define FMC_COMT	(1<<3)
-#define FMC_MERASE	(1<<2)
-#define FMC_ERASE	(1<<1)
-#define FMC_WRITE	(1<<0)
+#define FMC_WRKEY	(0xA442 << 16)
+#define FMC_COMT	(1 << 3)
+#define FMC_MERASE	(1 << 2)
+#define FMC_ERASE	(1 << 1)
+#define FMC_WRITE	(1 << 0)
 
 /* STELLARIS constants */
 
diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index 431d3b02..cc69dd16 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -1121,29 +1121,29 @@ static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx
 
 	if (strcmp(args[1], "SWWDG") == 0)
 	{
-		optionbyte |= (1<<0);
+		optionbyte |= (1 << 0);
 	}
 	else
 	{
-		optionbyte &= ~(1<<0);
+		optionbyte &= ~(1 << 0);
 	}
 
 	if (strcmp(args[2], "NORSTSTNDBY") == 0)
 	{
-		optionbyte |= (1<<1);
+		optionbyte |= (1 << 1);
 	}
 	else
 	{
-		optionbyte &= ~(1<<1);
+		optionbyte &= ~(1 << 1);
 	}
 
 	if (strcmp(args[3], "NORSTSTOP") == 0)
 	{
-		optionbyte |= (1<<2);
+		optionbyte |= (1 << 2);
 	}
 	else
 	{
-		optionbyte &= ~(1<<2);
+		optionbyte &= ~(1 << 2);
 	}
 
 	if (stm32x_erase_options(bank) != ERROR_OK)
diff --git a/src/flash/stm32x.h b/src/flash/stm32x.h
index 1b4c2d7d..51114667 100644
--- a/src/flash/stm32x.h
+++ b/src/flash/stm32x.h
@@ -64,21 +64,21 @@ typedef struct stm32x_flash_bank_s
 
 /* FLASH_CR register bits */
 
-#define FLASH_PG		(1<<0)
-#define FLASH_PER		(1<<1)
-#define FLASH_MER		(1<<2)
-#define FLASH_OPTPG		(1<<4)
-#define FLASH_OPTER		(1<<5)
-#define FLASH_STRT		(1<<6)
-#define FLASH_LOCK		(1<<7)
-#define FLASH_OPTWRE	(1<<9)
+#define FLASH_PG		(1 << 0)
+#define FLASH_PER		(1 << 1)
+#define FLASH_MER		(1 << 2)
+#define FLASH_OPTPG		(1 << 4)
+#define FLASH_OPTER		(1 << 5)
+#define FLASH_STRT		(1 << 6)
+#define FLASH_LOCK		(1 << 7)
+#define FLASH_OPTWRE	(1 << 9)
 
 /* FLASH_SR register bits */
 
-#define FLASH_BSY		(1<<0)
-#define FLASH_PGERR		(1<<2)
-#define FLASH_WRPRTERR	(1<<4)
-#define FLASH_EOP		(1<<5)
+#define FLASH_BSY		(1 << 0)
+#define FLASH_PGERR		(1 << 2)
+#define FLASH_WRPRTERR	(1 << 4)
+#define FLASH_EOP		(1 << 5)
 
 /* STM32_FLASH_OBR bit definitions (reading) */
 
diff --git a/src/flash/str7x.c b/src/flash/str7x.c
index 13b22be5..4068ad33 100644
--- a/src/flash/str7x.c
+++ b/src/flash/str7x.c
@@ -161,7 +161,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
 	
 	/* set default bits for str71x flash */
 	str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA1|FLASH_BSYA0);
-	str7x_info->disable_bit = (1<<1);
+	str7x_info->disable_bit = (1 << 1);
 	
 	if (strcmp(args[6], "STR71x") == 0)
 	{
@@ -175,7 +175,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
 	else if (strcmp(args[6], "STR75x") == 0)
 	{
 		str7x_info->register_base = 0x20100000;
-		str7x_info->disable_bit = (1<<0);
+		str7x_info->disable_bit = (1 << 0);
 	}
 	else
 	{
@@ -703,7 +703,7 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
 		flash_cmd = FLASH_SPR;
 		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
-		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1<<(15+ProtectionLevel)));
+		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1 << (15+ProtectionLevel)));
 		flash_cmd = FLASH_SPR | FLASH_WMS;
 		target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
 	}
diff --git a/src/flash/str9x.c b/src/flash/str9x.c
index 19c0f1ef..2b92d009 100644
--- a/src/flash/str9x.c
+++ b/src/flash/str9x.c
@@ -132,7 +132,7 @@ static int str9x_build_block_list(struct flash_bank_s *bank)
 		offset += bank->sectors[i].size;
 		bank->sectors[num_sectors].is_erased = -1;
 		bank->sectors[num_sectors].is_protected = 1;
-		str9x_info->sector_bits[num_sectors++] = (1<<i);
+		str9x_info->sector_bits[num_sectors++] = (1 << i);
 	}
 
 	for (i = 0; i < b1_sectors; i++)
@@ -143,9 +143,9 @@ static int str9x_build_block_list(struct flash_bank_s *bank)
 		bank->sectors[num_sectors].is_erased = -1;
 		bank->sectors[num_sectors].is_protected = 1;
 		if (str9x_info->variant)
-			str9x_info->sector_bits[num_sectors++] = (1<<i);
+			str9x_info->sector_bits[num_sectors++] = (1 << i);
 		else
-			str9x_info->sector_bits[num_sectors++] = (1<<(i+8));
+			str9x_info->sector_bits[num_sectors++] = (1 << (i+8));
 	}
 
 	return ERROR_OK;