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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-17 19:54:25 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-17 19:54:25 +0000 |
| commit | 8b994145b849c40b0a195c3fb332b9770b2f9097 (patch) | |
| tree | ac8decf22177a337ce4cce511a69638c5ddee20b /src/jtag/bitbang.c | |
| parent | 14cbd545bfca253a1c4063685eff6535e41d0611 (diff) | |
| download | openocd+libswd-8b994145b849c40b0a195c3fb332b9770b2f9097.tar.gz openocd+libswd-8b994145b849c40b0a195c3fb332b9770b2f9097.tar.bz2 openocd+libswd-8b994145b849c40b0a195c3fb332b9770b2f9097.tar.xz openocd+libswd-8b994145b849c40b0a195c3fb332b9770b2f9097.zip | |
Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/jtag/bitbang.c')
| -rw-r--r-- | src/jtag/bitbang.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/jtag/bitbang.c b/src/jtag/bitbang.c index 41ef061a..0be88b6f 100644 --- a/src/jtag/bitbang.c +++ b/src/jtag/bitbang.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * @@ -46,12 +46,12 @@ bitbang_interface_t *bitbang_interface; * Set this to 1 and str912 reset halt will fail. * * If someone can submit a patch with an explanation it will be greatly - * appreciated, but as far as I can tell (ØH) DCLK is generated upon + * appreciated, but as far as I can tell (ØH) DCLK is generated upon * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation! * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE * state". With hardware there is no such thing as *while* in a state. There * are only edges. So clk => 0 is in fact a very subtle state transition that - * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#& + * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#& * * For "reset halt" the last thing that happens before srst is asserted * is that the breakpoint is set up. If DCLK is not wiggled one last |