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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-18 10:22:44 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-18 10:22:44 +0000 |
| commit | a4c7e2dd965cad904b0ccedc9a8989f87173fb43 (patch) | |
| tree | 46164440cd88514e710413cb85701e0815d710fb /src/server/httpd/build.sh | |
| parent | 5badd9b29a40becea82c45c805e91fda49a6d560 (diff) | |
| download | openocd+libswd-a4c7e2dd965cad904b0ccedc9a8989f87173fb43.tar.gz openocd+libswd-a4c7e2dd965cad904b0ccedc9a8989f87173fb43.tar.bz2 openocd+libswd-a4c7e2dd965cad904b0ccedc9a8989f87173fb43.tar.xz openocd+libswd-a4c7e2dd965cad904b0ccedc9a8989f87173fb43.zip | |
David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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