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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-11-18 13:23:00 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-11-18 13:23:00 -0800
commit8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 (patch)
tree03fec2659ca4d6611168ab8d6eb100019a3204d1 /src/target/arm11.c
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ARM: setup "secure monitor mode" shadow regs
Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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