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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
| commit | ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc (patch) | |
| tree | 24c67ceb5f9a185a0e3220a3121d366c74b28aef /src/target/arm11.c | |
| parent | 6eee0729d79eab496d1d4368a2bae7e4e2d19876 (diff) | |
| download | openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.gz openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.bz2 openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.xz openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.zip | |
ARM DPM: share debug reason logic
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm11.c')
| -rw-r--r-- | src/target/arm11.c | 24 |
1 files changed, 7 insertions, 17 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c index b01e33bd..20ad22d5 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -83,8 +83,7 @@ static int arm11_check_init(struct arm11_common *arm11) */ arm11->arm.target->state = TARGET_HALTED; - arm11->arm.target->debug_reason = - arm11_get_DSCR_debug_reason(arm11->dscr); + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); } else { @@ -108,8 +107,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) int retval; arm11->arm.target->state = TARGET_HALTED; - arm11->arm.target->debug_reason = - arm11_get_DSCR_debug_reason(arm11->dscr); + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); /* REVISIT entire cache should already be invalid !!! */ register_cache_invalidate(arm11->arm.core_cache); @@ -551,20 +549,12 @@ static int arm11_resume(struct target *target, int current, i++; } + target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) - { - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_RUNNING; else - { - target->state = TARGET_DEBUG_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_DEBUG_RUNNING; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); return ERROR_OK; } @@ -728,7 +718,7 @@ static int arm11_step(struct target *target, int current, } - target->debug_reason = DBG_REASON_SINGLESTEP; + target->debug_reason = DBG_REASON_SINGLESTEP; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); |