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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
| commit | 6eee0729d79eab496d1d4368a2bae7e4e2d19876 (patch) | |
| tree | 0e6de2e7d924dc3d03861eb916bdfbce47e3d0b1 /src/target/arm11.h | |
| parent | eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb (diff) | |
| download | openocd+libswd-6eee0729d79eab496d1d4368a2bae7e4e2d19876.tar.gz openocd+libswd-6eee0729d79eab496d1d4368a2bae7e4e2d19876.tar.bz2 openocd+libswd-6eee0729d79eab496d1d4368a2bae7e4e2d19876.tar.xz openocd+libswd-6eee0729d79eab496d1d4368a2bae7e4e2d19876.zip | |
ARM11: use shared DSCR bit names
For the bits now defined in "arm_dpm.h", switch to the
shared DSCR_* symbol and remove the ARM11_DSCR_* version.
Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
sibling symbol. (Note: for both ARM11 and Cortex-A8, this
should arguably be enabled by default when single stepping.)
Remove some other unused declarations in "arm11.h".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm11.h')
| -rw-r--r-- | src/target/arm11.h | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/src/target/arm11.h b/src/target/arm11.h index b118e1c6..5f78db5d 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -38,6 +38,7 @@ } \ } while (0) +/* bits from ARMv7 DIDR */ enum arm11_debug_version { ARM11_DEBUG_V6 = 0x01, @@ -95,8 +96,6 @@ enum arm11_instructions enum arm11_dscr { - ARM11_DSCR_CORE_HALTED = 1 << 0, - ARM11_DSCR_CORE_RESTARTED = 1 << 1, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, @@ -105,20 +104,6 @@ enum arm11_dscr ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, - - ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, - ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, - ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11, - ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, - ARM11_DSCR_MODE_SELECT = 1 << 14, - ARM11_DSCR_WDTR_FULL = 1 << 29, - ARM11_DSCR_RDTR_FULL = 1 << 30, -}; - -enum arm11_cpsr -{ - ARM11_CPSR_T = 1 << 5, - ARM11_CPSR_J = 1 << 24, }; enum arm11_sc7 @@ -132,10 +117,4 @@ enum arm11_sc7 ARM11_SC7_WCR0 = 112, }; -struct arm11_reg_state -{ - uint32_t def_index; - struct target * target; -}; - #endif /* ARM11_H */ |