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authorDavid Brownell <dbrownell@users.sourceforge.net>2010-02-21 14:34:33 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2010-02-21 14:34:33 -0800
commit1aac72d24339380f6e98c50dec4c96ab30537749 (patch)
treeefd8b83082f072d807f168eabf415e1002cf5425 /src/target/arm720t.c
parenta299371a9ec109da3851cb43aed3e9157d095358 (diff)
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ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm720t.c')
-rw-r--r--src/target/arm720t.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index efafa5ee..2275935d 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -361,9 +361,9 @@ static int arm720t_soft_reset_halt(struct target *target)
armv4_5->cpsr->dirty = 1;
/* start fetching from 0x0 */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
arm720t_disable_mmu_caches(target, 1, 1, 1);
arm720t->armv4_5_mmu.mmu_enabled = 0;