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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-08-05 07:11:12 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-08-05 07:11:12 +0000
commit18293612537125c8864d4627c7c4b2b4ba7cc882 (patch)
treeac6aaec4091dad07099f0fad2445755c69d79418 /src/target/arm7_9_common.c
parent3a4896182036eb472a06f66be3710d5c228b6748 (diff)
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define resetting the target into the halted or running
state as an atomic operation. git-svn-id: svn://svn.berlios.de/openocd/trunk@888 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm7_9_common.c')
-rw-r--r--src/target/arm7_9_common.c35
1 files changed, 8 insertions, 27 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 117e9cb1..547bf3c4 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -815,6 +815,12 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_invalidate_core_regs(target);
+ if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+ {
+ /* debug entry was already prepared in arm7_9_assert_reset() */
+ target->debug_reason = DBG_REASON_DBGRQ;
+ }
+
return ERROR_OK;
}
@@ -832,13 +838,6 @@ int arm7_9_deassert_reset(target_t *target)
/* set up embedded ice registers again */
if ((retval=target->type->examine(target))!=ERROR_OK)
return retval;
-
- if (target->reset_halt)
- {
- /* halt the CPU as embedded ice was not set up in reset */
- if ((retval=target->type->halt(target))!=ERROR_OK)
- return retval;
- }
}
return retval;
}
@@ -975,9 +974,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int arm7_9_halt(target_t *target)
{
- if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0))
+ if (target->state==TARGET_RESET)
{
- LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset");
+ LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
return ERROR_OK;
}
@@ -998,24 +997,6 @@ int arm7_9_halt(target_t *target)
LOG_WARNING("target was in unknown state when halt was requested");
}
- if (target->state == TARGET_RESET)
- {
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
- {
- LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
- return ERROR_TARGET_FAILURE;
- }
- else
- {
- /* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in arm7_9_assert_reset()
- */
- target->debug_reason = DBG_REASON_DBGRQ;
-
- return ERROR_OK;
- }
- }
-
if (arm7_9->use_dbgrq)
{
/* program EmbeddedICE Debug Control Register to assert DBGRQ