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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-09 05:50:34 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-09 05:50:34 +0000
commita0647227439434c4a71470e336ec8715d43d0501 (patch)
treec32efbf7f71bf620ea2c1c72ed9e7f30b036727e /src/target/arm7_9_common.c
parent94320a1dc3394e90560fd4f0cddc3362a4337275 (diff)
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- added "init" command. "init" and "reset" at end of startup script is equivalent
to daemon_startup(still supported). - print warning if srst and trst change state at the same time when srst_and_trst is seperate - reset now performs a trst, examines and validates the jtag chain before targets assert reset - if startup fails to examine and validate the jtag chain, try a reset before trying again git-svn-id: svn://svn.berlios.de/openocd/trunk@552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm7_9_common.c')
-rw-r--r--src/target/arm7_9_common.c27
1 files changed, 17 insertions, 10 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index d77f2000..106b95db 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -755,6 +755,14 @@ int arm7_9_assert_reset(target_t *target)
if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
{
+ reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+
+ /* program EmbeddedICE Debug Control Register to deassert DBGRQ
+ * i.e. resume.
+ */
+ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
+ embeddedice_store_reg(dbg_ctrl);
+
/*
* Some targets do not support communication while SRST is asserted. We need to
* set up the reset vector catch here.
@@ -777,16 +785,6 @@ int arm7_9_assert_reset(target_t *target)
}
}
- /* we can't know what state the target is in as we might e.g.
- * be resetting after a power dropout, so we need to issue a tms/srst
- */
-
- /* assert SRST and TRST */
- /* system would get ouf sync if we didn't reset test-logic, too */
- jtag_add_reset(1, 1);
-
- jtag_add_sleep(5000);
-
/* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
@@ -965,6 +963,15 @@ int arm7_9_halt(target_t *target)
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
+ else
+ {
+ /* we came here in a reset_halt or reset_init sequence
+ * debug entry was already prepared in arm7_9_prepare_reset_halt()
+ */
+ target->debug_reason = DBG_REASON_DBGRQ;
+
+ return ERROR_OK;
+ }
}
if (arm7_9->use_dbgrq)