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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:37:21 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:37:21 -0800 |
| commit | 5706fd7860ea01c591ecf74880a5a5e04e6df22e (patch) | |
| tree | b67d26bb05820a933c132d97a3fc18e4aefd16db /src/target/arm920t.c | |
| parent | 60a2d85af1afbc207ae5fb9dafdbe4c8b49ad5bb (diff) | |
| download | openocd+libswd-5706fd7860ea01c591ecf74880a5a5e04e6df22e.tar.gz openocd+libswd-5706fd7860ea01c591ecf74880a5a5e04e6df22e.tar.bz2 openocd+libswd-5706fd7860ea01c591ecf74880a5a5e04e6df22e.tar.xz openocd+libswd-5706fd7860ea01c591ecf74880a5a5e04e6df22e.zip | |
ARM: simplify CPSR handling
Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.
This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).
This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm920t.c')
| -rw-r--r-- | src/target/arm920t.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 29f7917d..9cd491f3 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -452,7 +452,7 @@ int arm920t_arch_state(struct target *target) armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm920t->armv4_5_mmu.mmu_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -596,9 +596,9 @@ int arm920t_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3); + armv4_5->cpsr->dirty = 1; + armv4_5->cpsr->valid = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); |