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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 10:58:07 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 22:13:48 +0200 |
| commit | 6a237c23c1adb0be91a82a44d2cf13ff158b3ee2 (patch) | |
| tree | e83e5c8678c371be845fe9d00c4a9ef07038e8c9 /src/target/arm920t.c | |
| parent | 70fee9207b5fd1c6f499b790591446adc4d4467c (diff) | |
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arm: add error propagation for enable/disable mmu caches
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/target/arm920t.c')
| -rw-r--r-- | src/target/arm920t.c | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 9c11d124..a80a3781 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -333,14 +333,19 @@ int arm920t_get_ttb(struct target *target, uint32_t *result) } // EXPORTED to FA256 -void arm920t_disable_mmu_caches(struct target *target, int mmu, +int arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); - jtag_execute_queue(); + retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control &= ~0x1U; @@ -351,18 +356,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, if (i_cache) cp15_control &= ~0x1000U; - arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + return retval; } // EXPORTED to FA256 -void arm920t_enable_mmu_caches(struct target *target, int mmu, +int arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); - jtag_execute_queue(); + retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -373,7 +384,8 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu, if (i_cache) cp15_control |= 0x1000U; - arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); + return retval; } // EXPORTED to FA256 |