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authordrath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2007-06-14 09:47:00 +0000
committerdrath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2007-06-14 09:47:00 +0000
commit53d1f9b2ca5718e4996e9cf3406f857d0ed26df2 (patch)
tree76c0dbf27a9114fb6f8a4c9f71af6117716a05d5 /src/target/arm926ejs.c
parent7087b66f19a7d60025f7315baa26d682804f3640 (diff)
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- added manpage for OpenOCD (thanks to Uwe Hermann)
- fixed bug in ARM926EJ-S cache handling that caused cache linefills to be disabled after first debug entry - added support for auto image type detection (thanks to Vincent Palatin) - further work on ETM trace decoding (tested with a ETB interface using an ETM in normal 16-bit port mode, still experimental) git-svn-id: svn://svn.berlios.de/openocd/trunk@169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm926ejs.c')
-rw-r--r--src/target/arm926ejs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 89fbfae3..b62bc493 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -477,7 +477,7 @@ void arm926ejs_pre_restore_context(target_t *target)
/* read-modify-write CP15 cache debug control register
* to reenable I/D-cache linefills and disable WT */
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
- cache_dbg_ctrl |= 0x7;
+ cache_dbg_ctrl &= ~0x7;
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
}