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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-26 19:58:25 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-26 19:58:25 +0000 |
| commit | 3bcf8a8a25f7dbe3a958cb877d4e7d7160abb2bd (patch) | |
| tree | 74af094140182b30702a0498446f6484b372cb8f /src/target/arm_disassembler.c | |
| parent | fc318c02987ff87222d94a9f30d0f44d97554f0e (diff) | |
| download | openocd+libswd-3bcf8a8a25f7dbe3a958cb877d4e7d7160abb2bd.tar.gz openocd+libswd-3bcf8a8a25f7dbe3a958cb877d4e7d7160abb2bd.tar.bz2 openocd+libswd-3bcf8a8a25f7dbe3a958cb877d4e7d7160abb2bd.tar.xz openocd+libswd-3bcf8a8a25f7dbe3a958cb877d4e7d7160abb2bd.zip | |
David Brownell <david-b@pacbell.net> More fixes from test cases:
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm_disassembler.c')
| -rw-r--r-- | src/target/arm_disassembler.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index d961f96a..2c6cae16 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -3517,7 +3517,7 @@ static int t2ev_load_halfword(uint32_t opcode, uint32_t address, int rn = (opcode >> 16) & 0xf; int rt = (opcode >> 12) & 0xf; int op2 = (opcode >> 6) & 0x3f; - char *sign = (opcode & (1 < 24)) ? "S" : ""; + char *sign = ""; unsigned immed; if (rt == 0xf) { @@ -3525,6 +3525,9 @@ static int t2ev_load_halfword(uint32_t opcode, uint32_t address, return ERROR_OK; } + if (opcode & (1 << 24)) + sign = "S"; + if ((opcode & (1 << 23)) == 0) { if (rn == 0xf) { ldrh_literal: @@ -3547,16 +3550,16 @@ ldrh_literal: return ERROR_OK; } if ((op2 & 0x3c) == 0x38) { - immed = (opcode >> 4) & 0x3; + immed = opcode & 0xff; sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x", sign, rt, rn, immed, immed); return ERROR_OK; } if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) { - char *p1 = "]", *p2 = ""; + char *p1 = "", *p2 = "]"; immed = opcode & 0xff; - if (opcode & 0x200) + if (!(opcode & 0x200)) immed = -immed; /* two indexed modes will write back rn */ @@ -3577,8 +3580,9 @@ ldrh_literal: goto ldrh_literal; immed = opcode & 0xfff; - sprintf(cp, "LDR%sH.W\tr%d, [r%d, #%d]\t; %#6.6x", - sign, rt, rn, immed, immed); + sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x", + sign, *sign ? "" : ".W", + rt, rn, immed, immed); return ERROR_OK; } @@ -3653,7 +3657,7 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc retval = t2ev_load_word(opcode, address, instruction, cp); /* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */ - else if ((opcode & 0x1e700000) == 0x18e00000) + else if ((opcode & 0x1e700000) == 0x18300000) retval = t2ev_load_halfword(opcode, address, instruction, cp); /* ARMv7-M: A5.3.9 Load byte, memory hints */ |