ARM: standard disassembler uses Thumb2 entry

Tweak "standard" ARM disassembler diagnostics to fail if the target
is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for
cores inheriting this as the "generic" disassembler.

Also, to use the Thumb2 entry instead of the original Thumb entry.
This makes it work better for both newer cores (which support those
added instructions) and for BL and BLX instructions on older cores.
(Those instructions are 32-bits, which requires curious state-aware
code to go through a 16-bit decode interface...)

Plus minor cleanups, notably to have fewer exit paths and to make
sure they all return failure codes.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 6 insertions, 2 deletions

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 35c35203..b93df64d 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1784,8 +1784,12 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode,
 	}
 
 	/* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
-	 * these are effectively 32-bit instructions even in Thumb1.
-	 * Might be simplest to always use the Thumb2 decoder.
+	 * these are effectively 32-bit instructions even in Thumb1.  For
+	 * disassembly, it's simplest to always use the Thumb2 decoder.
+	 *
+	 * But some cores will evidently handle them as two instructions,
+	 * where exceptions may occur between the two.  The ETMv3.2+ ID
+	 * register has a bit which exposes this behavior.
 	 */
 
 	snprintf(instruction->text, 128,