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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
| commit | ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc (patch) | |
| tree | 24c67ceb5f9a185a0e3220a3121d366c74b28aef /src/target/arm_dpm.c | |
| parent | 6eee0729d79eab496d1d4368a2bae7e4e2d19876 (diff) | |
| download | openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.gz openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.bz2 openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.tar.xz openocd+libswd-ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc.zip | |
ARM DPM: share debug reason logic
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm_dpm.c')
| -rw-r--r-- | src/target/arm_dpm.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index ca3930fc..b02baa39 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -756,6 +756,42 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) /*----------------------------------------------------------------------*/ /* + * Other debug and support utilities + */ + +void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) +{ + struct target *target = dpm->arm->target; + + dpm->dscr = dscr; + + /* Examine debug reason */ + switch (DSCR_ENTRY(dscr)) { + case 6: /* Data abort (v6 only) */ + case 7: /* Prefetch abort (v6 only) */ + /* FALL THROUGH -- assume a v6 core in abort mode */ + case 0: /* HALT request from debugger */ + case 4: /* EDBGRQ */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 1: /* HW breakpoint */ + case 3: /* SW BKPT */ + case 5: /* vector catch */ + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 2: /* asynch watchpoint */ + case 10: /* precise watchpoint */ + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + default: + target->debug_reason = DBG_REASON_UNDEFINED; + break; + } +} + +/*----------------------------------------------------------------------*/ + +/* * Setup and management support. */ |