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authorDavid Brownell <dbrownell@users.sourceforge.net>2010-02-21 14:34:33 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2010-02-21 14:34:33 -0800
commit1aac72d24339380f6e98c50dec4c96ab30537749 (patch)
treeefd8b83082f072d807f168eabf415e1002cf5425 /src/target/arm_semihosting.c
parenta299371a9ec109da3851cb43aed3e9157d095358 (diff)
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ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm_semihosting.c')
-rw-r--r--src/target/arm_semihosting.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 9b853d9f..24a4de57 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -393,8 +393,8 @@ static int do_semihosting(struct target *target)
armv4_5->core_cache->reg_list[0].dirty = 1;
/* LR --> PC */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
- armv4_5->core_cache->reg_list[15].dirty = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, lr);
+ armv4_5->pc->dirty = 1;
/* saved PSR --> current PSR */
buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
@@ -429,7 +429,7 @@ int arm_semihosting(struct target *target, int *retval)
return 0;
/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
- r = arm->core_cache->reg_list + 15;
+ r = arm->pc;
pc = buf_get_u32(r->value, 0, 32);
if (pc != 0x00000008 && pc != 0xffff0008)
return 0;