summaryrefslogtreecommitdiff
path: root/src/target/arm_semihosting.c
diff options
context:
space:
mode:
authorDavid Brownell <dbrownell@users.sourceforge.net>2009-12-04 20:14:46 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-12-04 20:14:46 -0800
commit340e2eb7629fc1fdb6d2ead2952982584abdcefa (patch)
tree8522b7288d8d8e8e763084d27882d5c7b13662e3 /src/target/arm_semihosting.c
parente51b9a4ac7afa0fde11690268ba88861e1000f60 (diff)
downloadopenocd+libswd-340e2eb7629fc1fdb6d2ead2952982584abdcefa.tar.gz
openocd+libswd-340e2eb7629fc1fdb6d2ead2952982584abdcefa.tar.bz2
openocd+libswd-340e2eb7629fc1fdb6d2ead2952982584abdcefa.tar.xz
openocd+libswd-340e2eb7629fc1fdb6d2ead2952982584abdcefa.zip
ARM: misc generic cleanup
Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm_semihosting.c')
-rw-r--r--src/target/arm_semihosting.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index d71fbaef..39625f61 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -379,15 +379,22 @@ static int do_semihosting(struct target *target)
}
/* resume execution to the original mode */
+
+ /* return value in R0 */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
armv4_5->core_cache->reg_list[0].dirty = 1;
+
+ /* LR --> PC */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
armv4_5->core_cache->reg_list[15].dirty = 1;
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+ /* saved PSR --> current PSR */
+ buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
+ armv4_5->cpsr->dirty = 1;
armv4_5->core_mode = spsr & 0x1f;
if (spsr & 0x20)
armv4_5->core_state = ARM_STATE_THUMB;
+
return target_resume(target, 1, 0, 0, 0);
}