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| author | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-14 16:33:52 +0000 |
|---|---|---|
| committer | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-14 16:33:52 +0000 |
| commit | 699d246b1c7880d6817f06f31561026f9322ce49 (patch) | |
| tree | 215848a2880025b68d980d6f81777f51c6da0d13 /src/target/arm_simulator.c | |
| parent | aed582e4228f3ca60d47bc79f86447c01ba686b5 (diff) | |
| download | openocd+libswd-699d246b1c7880d6817f06f31561026f9322ce49.tar.gz openocd+libswd-699d246b1c7880d6817f06f31561026f9322ce49.tar.bz2 openocd+libswd-699d246b1c7880d6817f06f31561026f9322ce49.tar.xz openocd+libswd-699d246b1c7880d6817f06f31561026f9322ce49.zip | |
Solve problem with single stepping.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1455 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm_simulator.c')
| -rw-r--r-- | src/target/arm_simulator.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 217633e8..b21ea4a8 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -415,7 +415,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) u8 carry_out; Rd = 0x0; - Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32); + /* ARM_MOV and ARM_MVN does not use Rn */ + if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN)) + Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32); + else + Rn = 0; + shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out); /* adjust Rn in case the PC is being read */ @@ -446,6 +451,8 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) Rd = shifter_operand; else if (instruction.type == ARM_MVN) Rd = ~shifter_operand; + else + LOG_WARNING("unhandled instruction type"); if (dry_run_pc) { |