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| author | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-03 10:10:12 +0000 |
|---|---|---|
| committer | mlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-04-03 10:10:12 +0000 |
| commit | 47a81338a592084ad4be9e49ba076192e93d6260 (patch) | |
| tree | f9b0980e4900f440d09155bf80c05bc51d2537a4 /src/target/armv4_5.c | |
| parent | 9646f21ad8288f8a4fa6d260e949e599f3978939 (diff) | |
| download | openocd+libswd-47a81338a592084ad4be9e49ba076192e93d6260.tar.gz openocd+libswd-47a81338a592084ad4be9e49ba076192e93d6260.tar.bz2 openocd+libswd-47a81338a592084ad4be9e49ba076192e93d6260.tar.xz openocd+libswd-47a81338a592084ad4be9e49ba076192e93d6260.zip | |
Slight improvement in run_algorithm register restore.
More debug info for cortex swjdp errors.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1453 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/armv4_5.c')
| -rw-r--r-- | src/target/armv4_5.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index cf0632f1..99f93bde 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -661,10 +661,15 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem for (i = 0; i <= 16; i++) { - LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1; + u32 regvalue; + regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32); + if (regvalue != context[i]) + { + LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]); + buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]); + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1; + } } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; |