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authorZachary T Welch <zw@superlucidity.net>2009-11-13 09:43:03 -0800
committerZachary T Welch <zw@superlucidity.net>2009-11-13 11:58:13 -0800
commitaf949b2531d2a8863d077025db40cbb170d13a63 (patch)
treec8d57d3b5f220c6fbb6a9d6a1cb206cd2cfd85a9 /src/target/armv4_5.h
parentd0c19e0a9d51211953a363026c662d290542fe85 (diff)
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armv4_5_common_t -> struct arm
Remove misleading typedef and just use struct arm.
Diffstat (limited to 'src/target/armv4_5.h')
-rw-r--r--src/target/armv4_5.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 3c65069e..9823f4e6 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -84,7 +84,7 @@ enum
* Cortex-M series cores do not support as many core states or shadowed
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
-typedef struct arm
+struct arm
{
int common_magic;
struct reg_cache *core_cache;
@@ -104,7 +104,7 @@ typedef struct arm
int (*write_core_reg)(struct target_s *target,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
-} armv4_5_common_t;
+};
#define target_to_armv4_5 target_to_arm
@@ -132,11 +132,11 @@ struct armv4_5_core_reg
int num;
enum armv4_5_mode mode;
target_t *target;
- armv4_5_common_t *armv4_5_common;
+ struct arm *armv4_5_common;
};
struct reg_cache* armv4_5_build_reg_cache(target_t *target,
- armv4_5_common_t *armv4_5_common);
+ struct arm *armv4_5_common);
/* map psr mode bits to linear number */
static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -180,7 +180,7 @@ int armv4_5_get_gdb_reg_list(target_t *target,
reg_t **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
int armv4_5_run_algorithm(struct target_s *target,
int num_mem_params, struct mem_param *mem_params,