- endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts

- added access to ARM920T vector catch register (via generic register mechanism)
- don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache
- read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands)
- memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes)
- made in_handler independent from in field (makes the handler more flexible)
- added timeout to ft2232 when using D2XX library
- fixed STR7x protection bit handling on second bank (thanks to Bernard)
- added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen)
- fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen)


git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 8 insertions, 0 deletions

diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 766718b6..03b95935 100644
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -46,4 +46,12 @@ extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *cac
 
 extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
 
+enum
+{
+	ARMV4_5_D_U_CACHE_ENABLED = 0x4,
+	ARMV4_5_I_CACHE_ENABLED = 0x1000,
+	ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
+	ARMV4_5_CACHE_RR_BIT = 0x5000,
+};
+
 #endif /* ARMV4_5_CACHE_H */