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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 10:58:07 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 22:13:48 +0200 |
| commit | 6a237c23c1adb0be91a82a44d2cf13ff158b3ee2 (patch) | |
| tree | e83e5c8678c371be845fe9d00c4a9ef07038e8c9 /src/target/armv4_5_mmu.c | |
| parent | 70fee9207b5fd1c6f499b790591446adc4d4467c (diff) | |
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arm: add error propagation for enable/disable mmu caches
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/target/armv4_5_mmu.c')
| -rw-r--r-- | src/target/armv4_5_mmu.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index 3d450ae1..8978f354 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -131,14 +131,20 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common * return ERROR_TARGET_NOT_HALTED; /* disable MMU and data (or unified) cache */ - armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); + retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); + if (retval !=ERROR_OK) + return retval; retval = armv4_5_mmu->read_memory(target, address, size, count, buffer); + if (retval !=ERROR_OK) + return retval; /* reenable MMU / cache */ - armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, + retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); + if (retval !=ERROR_OK) + return retval; return retval; } @@ -151,14 +157,20 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common return ERROR_TARGET_NOT_HALTED; /* disable MMU and data (or unified) cache */ - armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); + retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); + if (retval !=ERROR_OK) + return retval; retval = armv4_5_mmu->write_memory(target, address, size, count, buffer); + if (retval !=ERROR_OK) + return retval; /* reenable MMU / cache */ - armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, + retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); + if (retval !=ERROR_OK) + return retval; return retval; } |