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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-11-22 03:37:21 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-11-22 03:37:21 -0800
commit5706fd7860ea01c591ecf74880a5a5e04e6df22e (patch)
treeb67d26bb05820a933c132d97a3fc18e4aefd16db /src/target/armv7a.c
parent60a2d85af1afbc207ae5fb9dafdbe4c8b49ad5bb (diff)
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ARM: simplify CPSR handling
Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/armv7a.c')
-rw-r--r--src/target/armv7a.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index ea883c16..63f95b84 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -74,8 +74,7 @@ int armv7a_arch_state(struct target *target)
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache
- ->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[armv7a->armv4_5_mmu.mmu_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],