David Brownell <david-b@pacbell.net>:

Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 4 insertions, 10 deletions

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 17e3ff38..ec90b715 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -61,15 +61,10 @@ enum
 	ARMV7M_xPSR = 16,
 	ARMV7M_MSP,
 	ARMV7M_PSP,
-
-	/* FIXME the register numbers here are core-specific.  Cortex-M3
-	 * through r1p1 only defines registers up to PSP; see ARM DDI 0337E.
-	 *
-	 * It's r2p0 (see ARM DDI 0337G) which defines the register that's
-	 * called SPEC20 here, with four single-byte fields with CONTROL
-	 * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte).
-	 */
-	ARMV7M_SPEC20 = 20,
+	ARMV7M_PRIMASK,
+	ARMV7M_BASEPRI,
+	ARMV7M_FAULTMASK,
+	ARMV7M_CONTROL,
 	ARMV7NUMCOREREGS
 };
 
@@ -83,7 +78,6 @@ typedef struct armv7m_common_s
 	int exception_number;
 	swjdp_common_t swjdp_info;
 
-	bool has_spec20;
 
 	/* Direct processor core register read and writes */
 	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);