initial SWD transport (SWD infrastructure #2)

This piggy backs on JTAG so it's not yet pretty, but that
seems unavoidable so far given today's OpenOCD internals.

SWD init and data transfer  are unfinished and untested, but
that should cause no regressions, and will be addressed by
the time drivers start using this infrastructure.  Checking
in whould get the code working better sooner, and turn up any
structural/architectural issues while they're easier to fix.

The debug adapter drivers will provide simple SWD driver
structs with methods that kick in as needed (instead of JTAG).
So far just one adapter driver has been updated (not yet
ready to use or circulate).

The biggest issues are probably
  - fault handling, where the ARM Debug Interface V5 pipelining
    needs work in both JTAG and SWD modes and
  - missing  rewrite of block I/O code to work on both of our
Cortex-ready transports (Current code is  hard-wired to JTAG);
relates also to the pipelining issue.
  - omitted support to activate/deactivate SWO/SWV trace (this is
    technically trivial, but configuring what to trace is NOT.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
----

 doc/openocd.texi        |   17 ++
 src/jtag/core.c         |    3
 src/jtag/interface.h    |    4
 src/jtag/jtag.h         |    2
 src/jtag/swd.h          |  114 +++++++++++++++++++
 src/jtag/tcl.c          |    2
 src/target/adi_v5_swd.c |  281 ++++++++++++++++++++++++++++++++++++++++++++++--
 src/target/arm_adi_v5.c |    8 +
 src/target/arm_adi_v5.h |    3
 9 files changed, 425 insertions(+), 9 deletions(-)

0 files changed, 0 insertions, 0 deletions