ARM DPM: share debug reason logic

No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.

Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that.  Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.

Likewise with private copies of DSCR ... add one to the DPM
struct.  Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 12 insertions, 25 deletions

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 14cbb9d7..eb42a5d5 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -782,7 +782,7 @@ static int cortex_a8_resume(struct target *target, int current,
 static int cortex_a8_debug_entry(struct target *target)
 {
 	int i;
-	uint32_t regfile[16], wfar, cpsr, dscr;
+	uint32_t regfile[16], cpsr, dscr;
 	int retval = ERROR_OK;
 	struct working_area *regfile_working_area = NULL;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -793,6 +793,7 @@ static int cortex_a8_debug_entry(struct target *target)
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+	/* REVISIT surely we should not re-read DSCR !! */
 	mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
@@ -807,30 +808,16 @@ static int cortex_a8_debug_entry(struct target *target)
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 
 	/* Examine debug reason */
-	switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
-	{
-		case 0:		/* DRCR[0] write */
-		case 4:		/* EDBGRQ */
-			target->debug_reason = DBG_REASON_DBGRQ;
-			break;
-		case 1:		/* HW breakpoint */
-		case 3:		/* SW BKPT */
-		case 5:		/* vector catch */
-			target->debug_reason = DBG_REASON_BREAKPOINT;
-			break;
-		case 2:		/* asynch watchpoint */
-		case 10:	/* precise watchpoint */
-			target->debug_reason = DBG_REASON_WATCHPOINT;
-
-			/* save address of faulting instruction */
-			retval = mem_ap_read_atomic_u32(swjdp,
-					armv7a->debug_base + CPUDBG_WFAR,
-					&wfar);
-			arm_dpm_report_wfar(&armv7a->dpm, wfar);
-			break;
-		default:
-			target->debug_reason = DBG_REASON_UNDEFINED;
-			break;
+	arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+	/* save address of instruction that triggered the watchpoint? */
+	if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+		uint32_t wfar;
+
+		retval = mem_ap_read_atomic_u32(swjdp,
+				armv7a->debug_base + CPUDBG_WFAR,
+				&wfar);
+		arm_dpm_report_wfar(&armv7a->dpm, wfar);
 	}
 
 	/* REVISIT fast_reg_read is never set ... */