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| author | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:56:56 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:56:56 -0800 |
| commit | 3b68a708c2b039d9b091608eccb2206725742a47 (patch) | |
| tree | 5698d4d62a09c3c1b28cccd2a1c07cd287528c86 /src/target/cortex_m3.c | |
| parent | ecff73043c1ddcc97d4d1ea1c87f251a850b22d4 (diff) | |
| download | openocd+libswd-3b68a708c2b039d9b091608eccb2206725742a47.tar.gz openocd+libswd-3b68a708c2b039d9b091608eccb2206725742a47.tar.bz2 openocd+libswd-3b68a708c2b039d9b091608eccb2206725742a47.tar.xz openocd+libswd-3b68a708c2b039d9b091608eccb2206725742a47.zip | |
ADIv5: remove ATOMIC/COMPOSITE interface mode
This removes context-sensitivity from the programming interface and makes
it possible to know what a block of code does without needing to know the
previous history (specifically, the DAP's "trans_mode" setting).
The mode was only set to ATOMIC briefly after DAP initialization, making
this patch be primarily cleanup; almost everything depends on COMPOSITE.
The transactions which shouldn't have been queued were already properly
flushing the queue.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_m3.c')
| -rw-r--r-- | src/target/cortex_m3.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 3dd94685..3ebc34ad 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -70,8 +70,6 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); @@ -101,8 +99,6 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp, mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); |