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| author | David Brownell <dbrownell@users.sourceforge.net> | 2010-01-29 14:31:19 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-01-29 14:31:19 -0800 |
| commit | 3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce (patch) | |
| tree | 663721b79ee3d87a478c49525b484aef3812855c /src/target/cortex_m3.c | |
| parent | 2248c387f2c413c89d0f175b464a6e60ea20e75b (diff) | |
| download | openocd+libswd-3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce.tar.gz openocd+libswd-3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce.tar.bz2 openocd+libswd-3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce.tar.xz openocd+libswd-3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce.zip | |
ADIv5: cleanup, rename swjdp_transaction_endcheck()
Make messages reference "DAP" if they're actually transport-agnostic, or
"JTAG-DP" when they're JTAG-specific. Saying SWJ-DP is often wrong (on
most Cortex-A8 chips) and is confusing even if correct (since we don't
yet support SWD).
Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight
that it's JTAG-specific, and that identify DAP clients undesirably depending
on JTAG. (They will all need to change for SWD support.)
Shrink a few overlong lines of code. Copy a comment from code removed
in a previous patch (for the ARMv7-M "dap baseaddr" command).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_m3.c')
| -rw-r--r-- | src/target/cortex_m3.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 3bbe42c9..3f347697 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -80,7 +80,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); /* restore DCB_DCRDR - this needs to be in a seperate * transaction otherwise the emulated DCC channel breaks */ @@ -111,7 +111,7 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp, dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); - retval = swjdp_transaction_endcheck(swjdp); + retval = jtagdp_transaction_endcheck(swjdp); /* restore DCB_DCRDR - this needs to be in a seperate * transaction otherwise the emulated DCC channel breaks */ @@ -238,7 +238,7 @@ static int cortex_m3_endreset_event(struct target *target) target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, dwt_list[i].function); } - swjdp_transaction_endcheck(swjdp); + jtagdp_transaction_endcheck(swjdp); register_cache_invalidate(cortex_m3->armv7m.core_cache); @@ -317,7 +317,7 @@ static int cortex_m3_examine_exception_reason(struct target *target) except_sr = 0; break; } - swjdp_transaction_endcheck(swjdp); + jtagdp_transaction_endcheck(swjdp); LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \ shcsr, except_sr, cfsr, except_ar); return ERROR_OK; |