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authorntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-02 21:06:12 +0000
committerntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-02 21:06:12 +0000
commit7dc29156fee5d4ae30f65f4c82e8cefde763fe40 (patch)
tree92e7080d9093d40bf08fc11f5686dacfab0e8abd /src/target/cortex_m3.c
parent88b5c6da2a2a59fcb1eb3da22ed5339b8e0f35cd (diff)
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- change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use swjdp_common_t *swjdp instead of arm_jtag_t *jtag_info
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs. - add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus - Set default memaccess value to 8 for Cortex-M3. - Add dap memaccess command. - document all armv7 dap cmds. - Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu]. git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_m3.c')
-rw-r--r--src/target/cortex_m3.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 68a23c0f..40aadea2 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1564,9 +1564,12 @@ int cortex_m3_handle_target_request(void *priv)
int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
{
+ int retval;
armv7m_common_t *armv7m;
armv7m = &cortex_m3->armv7m;
+ armv7m_init_arch_info(target, armv7m);
+
/* prepare JTAG information for the new target */
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
@@ -1575,6 +1578,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
armv7m->swjdp_info.ap_csw_value = -1;
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
+ armv7m->swjdp_info.memaccess_tck = 8;
/* initialize arch-specific breakpoint handling */
@@ -1590,13 +1594,17 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
armv7m->pre_restore_context = NULL;
armv7m->post_restore_context = NULL;
- armv7m_init_arch_info(target, armv7m);
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
+ if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
+ {
+ return retval;
+ }
+
return ERROR_OK;
}