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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-05 01:03:54 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-05 01:03:54 -0800 |
| commit | 8fb2baaa6b428bd50165f045749786c34857ab02 (patch) | |
| tree | 2ece78c238da0ac617b443303a45e0711a1a9060 /src/target/cortex_m3.c | |
| parent | 7acb2607ff79336174014ddfc313433ada9abc44 (diff) | |
| download | openocd+libswd-8fb2baaa6b428bd50165f045749786c34857ab02.tar.gz openocd+libswd-8fb2baaa6b428bd50165f045749786c34857ab02.tar.bz2 openocd+libswd-8fb2baaa6b428bd50165f045749786c34857ab02.tar.xz openocd+libswd-8fb2baaa6b428bd50165f045749786c34857ab02.zip | |
Cortex-M3: minor cleanup
There's no reason to read which interrupts are enabled from
the NVIC; that state isn't used. Plus, it's highly dynamic
since firmware can change it at any time; remove the support
for those state records.
Remove duplicate definition of DWT_CTRL address; shrink a line.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_m3.c')
| -rw-r--r-- | src/target/cortex_m3.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index ef57a4cd..d8a28796 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -1495,7 +1495,7 @@ static int cortex_m3_init_target(struct command_context_s *cmd_ctx, static int cortex_m3_examine(struct target_s *target) { int retval; - uint32_t cpuid, fpcr, dwtcr, ictr; + uint32_t cpuid, fpcr, dwtcr; int i; /* get pointers to arch-specific information */ @@ -1511,21 +1511,15 @@ static int cortex_m3_examine(struct target_s *target) target_set_examined(target); /* Read from Device Identification Registers */ - if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + retval = target_read_u32(target, CPUID, &cpuid); + if (retval != ERROR_OK) return retval; if (((cpuid >> 4) & 0xc3f) == 0xc23) LOG_DEBUG("CORTEX-M3 processor detected"); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]); - } + /* NOTE: FPB and DWT are both optional. */ /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); |