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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 13:45:53 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 22:13:49 +0200 |
| commit | e7a1ec64bface364305e9c355811838e9f310bf3 (patch) | |
| tree | 0b8b84d7c6a32d48bd516216e2e7560e06d37f7b /src/target/cortex_m3.c | |
| parent | 44ef0327dd97c1893afc63cd7fd8025cb1b57827 (diff) | |
| download | openocd+libswd-e7a1ec64bface364305e9c355811838e9f310bf3.tar.gz openocd+libswd-e7a1ec64bface364305e9c355811838e9f310bf3.tar.bz2 openocd+libswd-e7a1ec64bface364305e9c355811838e9f310bf3.tar.xz openocd+libswd-e7a1ec64bface364305e9c355811838e9f310bf3.zip | |
arm_adi_v5: add error propagation for dap_setup_accessport
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/target/cortex_m3.c')
| -rw-r--r-- | src/target/cortex_m3.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 4f3560f7..d6090f55 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -71,13 +71,17 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); if (retval != ERROR_OK) return retval; /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); if (retval != ERROR_OK) return retval; @@ -106,12 +110,16 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); // XXX check retval /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); // XXX check retval |