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authorntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-28 20:05:17 +0000
committerntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-04-28 20:05:17 +0000
commitf2e10a60506a04b811ac52e85084986d9ae46725 (patch)
tree0847408f4172dd9cce7505aab0312af1c95f070d /src/target/cortex_m3.c
parentcab29a63de935871135a6ee0ed9d29d5edea0f27 (diff)
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- add cortex_m3 variant luminary to fix reset issue with asserting SRST
- https://lists.berlios.de/pipermail/openocd-development/2008-April/002022.html for details git-svn-id: svn://svn.berlios.de/openocd/trunk@624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_m3.c')
-rw-r--r--src/target/cortex_m3.c28
1 files changed, 25 insertions, 3 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 803f05ce..1f9674fa 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -706,13 +706,26 @@ int cortex_m3_assert_reset(target_t *target)
ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
}
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ /* following hack is to handle luminary reset
+ * when srst is asserted the luminary device seesm to also clear the debug registers
+ * which does not match the armv7 debug TRM */
+
+ if (strcmp(cortex_m3->variant, "luminary") == 0)
{
- jtag_add_reset(1, 1);
+ /* this causes the luminary device to reset using the watchdog */
+ ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
+ LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
}
else
{
- jtag_add_reset(0, 1);
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ {
+ jtag_add_reset(1, 1);
+ }
+ else
+ {
+ jtag_add_reset(0, 1);
+ }
}
target->state = TARGET_RESET;
@@ -1438,6 +1451,15 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
armv7m->pre_restore_context = NULL;
armv7m->post_restore_context = NULL;
+ if (variant)
+ {
+ cortex_m3->variant = strdup(variant);
+ }
+ else
+ {
+ cortex_m3->variant = strdup("");
+ }
+
armv7m_init_arch_info(target, armv7m);
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;