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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-07 10:54:43 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-07 10:54:43 +0000 |
| commit | 96261e827782235709fcdfb2c1bbb93fedc977be (patch) | |
| tree | 3faadd8ec22c735a44b38cc3e73a0cdbae364e98 /src/target/event | |
| parent | c317ffe2435236754a80c856dee688cb09ac425e (diff) | |
| download | openocd+libswd-96261e827782235709fcdfb2c1bbb93fedc977be.tar.gz openocd+libswd-96261e827782235709fcdfb2c1bbb93fedc977be.tar.bz2 openocd+libswd-96261e827782235709fcdfb2c1bbb93fedc977be.tar.xz openocd+libswd-96261e827782235709fcdfb2c1bbb93fedc977be.zip | |
wi-9c target scripts
git-svn-id: svn://svn.berlios.de/openocd/trunk@464 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/event')
| -rw-r--r-- | src/target/event/wi-9c_reset.script | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/target/event/wi-9c_reset.script b/src/target/event/wi-9c_reset.script new file mode 100644 index 00000000..cd483701 --- /dev/null +++ b/src/target/event/wi-9c_reset.script @@ -0,0 +1,56 @@ +mww 0x90600104 0x33313333
+mww 0xA0700000 0x00000001 # Enable the memory controller.
+mww 0xA0700024 0x00000006 # Set the refresh counter 6
+mww 0xA0700028 0x00000001 #
+mww 0xA0700030 0x00000001 # Set the precharge period
+mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
+mww 0xA070003C 0x00000001 # tAPR
+mww 0xA0700040 0x00000005 # tDAL
+mww 0xA0700044 0x00000001 # tWR
+mww 0xA0700048 0x00000006 # tRC 32 clock cycles
+mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
+mww 0xA0700054 0x00000001 # tRRD
+mww 0xA0700058 0x00000001 # tMRD
+mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
+mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
+mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
+mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
+#
+mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
+mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
+mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
+mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
+#
+mww 0xA0700020 0x00000103 # issue SDRAM PALL command
+#
+mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
+#
+# Add some dummy writes to give the SDRAM time to settle, it needs two
+# AHB clock cycles, here we poke in the debugger flag, this lets
+# the software know that we are in the debugger
+mww 0xA0900000 0x00000002
+mww 0xA0900000 0x00000002
+mww 0xA0900000 0x00000002
+mww 0xA0900000 0x00000002
+mww 0xA0900000 0x00000002
+#
+mdw 0xA0900000
+mdw 0xA0900000
+mdw 0xA0900000
+mdw 0xA0900000
+mdw 0xA0900000
+#
+mww 0xA0700024 0x00000030 # Set the refresh counter to 30
+mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+#
+# Next we perform a read of RAM.
+# mw = move word.
+mdw 0x00022000
+# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
+#
+mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
+mww 0xA0700100 0x00084280 # Enable buffer access
+mww 0xA0700120 0x00084280 # Enable buffer access
+mww 0xA0700140 0x00084280 # Enable buffer access
+mww 0xA0700160 0x00084280 # Enable buffer access
+
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