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| author | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:34:33 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:34:33 -0800 |
| commit | 1aac72d24339380f6e98c50dec4c96ab30537749 (patch) | |
| tree | efd8b83082f072d807f168eabf415e1002cf5425 /src/target/feroceon.c | |
| parent | a299371a9ec109da3851cb43aed3e9157d095358 (diff) | |
| download | openocd+libswd-1aac72d24339380f6e98c50dec4c96ab30537749.tar.gz openocd+libswd-1aac72d24339380f6e98c50dec4c96ab30537749.tar.bz2 openocd+libswd-1aac72d24339380f6e98c50dec4c96ab30537749.tar.xz openocd+libswd-1aac72d24339380f6e98c50dec4c96ab30537749.zip | |
ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.
For XScale, fix a dodgy sequence while stepping. It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic. It
should have done like ARM7/ARM9 does: init to NULL.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/feroceon.c')
| -rw-r--r-- | src/target/feroceon.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 19ed0cd5..e0c3c395 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -337,7 +337,7 @@ void feroceon_branch_resume_thumb(struct target *target) struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -519,7 +519,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t /* backup clobbered processor state */ for (i = 0; i <= 5; i++) save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32); - save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + save[i] = buf_get_u32(armv4_5->pc->value, 0, 32); /* set up target address in r0 */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); @@ -572,9 +572,9 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t armv4_5->core_cache->reg_list[i].valid = 1; armv4_5->core_cache->reg_list[i].dirty = 1; } - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]); - armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_cache->reg_list[15].dirty = 1; + buf_set_u32(armv4_5->pc->value, 0, 32, save[i]); + armv4_5->pc->valid = 1; + armv4_5->pc->dirty = 1; armv4_5->core_state = core_state; return retval; |