diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:21:48 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:27:29 -0800 |
| commit | b404b9ab57f17d84eb8dbfb42e6ac49c32913eee (patch) | |
| tree | 4416b9f407908e7554dc8b2f5329c4461dfa9516 /src/target/mips32.h | |
| parent | fa618cc74deea6741c745b4f80dace2421209a1e (diff) | |
| download | openocd+libswd-b404b9ab57f17d84eb8dbfb42e6ac49c32913eee.tar.gz openocd+libswd-b404b9ab57f17d84eb8dbfb42e6ac49c32913eee.tar.bz2 openocd+libswd-b404b9ab57f17d84eb8dbfb42e6ac49c32913eee.tar.xz openocd+libswd-b404b9ab57f17d84eb8dbfb42e6ac49c32913eee.zip | |
ARM: use arm_reg_current()
Start using the arm_reg_current() call. This shrinks and speeds
the affected code. It can also prevent some coredumps coming from
invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns
bogus registers if e.g. "Secure Monitor" mode isn't supported by
the current CPU.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/mips32.h')
0 files changed, 0 insertions, 0 deletions