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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
| commit | c0787b699496080d48174713a0b30e81ef5db3be (patch) | |
| tree | 9dab9d70f9d87a6505592ae5484dfe0686d3ccbe /src/target/mips32.h | |
| parent | 368daf44ff6aecb522952872a44bcf9e26b836f3 (diff) | |
| download | openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.gz openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.bz2 openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.xz openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.zip | |
- correct the register hi/lo read - wrong way round
- all the register now can be written to, including the special CP0 regs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/mips32.h')
| -rw-r--r-- | src/target/mips32.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/target/mips32.h b/src/target/mips32.h index a7a98b5c..9018d85c 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -66,7 +66,9 @@ typedef struct mips32_core_reg_s #define MIPS32_OP_LBU 0x24 #define MIPS32_OP_LHU 0x25 #define MIPS32_OP_MFHI 0x10 +#define MIPS32_OP_MTHI 0x11 #define MIPS32_OP_MFLO 0x12 +#define MIPS32_OP_MTLO 0x13 #define MIPS32_OP_SB 0x28 #define MIPS32_OP_SH 0x29 #define MIPS32_OP_SW 0x2B @@ -90,8 +92,10 @@ typedef struct mips32_core_reg_s #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off) #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val) #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off) -#define MIPS32_LO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) -#define MIPS32_HI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) +#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO) +#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI) +#define MIPS32_MTLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO) +#define MIPS32_MTHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI) #define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) |