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| author | Spencer Oliver <ntfreak@users.sourceforge.net> | 2010-03-17 17:24:22 +0000 |
|---|---|---|
| committer | Spencer Oliver <ntfreak@users.sourceforge.net> | 2010-03-18 09:19:39 +0000 |
| commit | b48a94f05da3a887f1978da01db77b79513d4aa9 (patch) | |
| tree | 9abca54be55e31e79d88c6af0f46e7fcbdb40745 /src/target/mips_m4k.c | |
| parent | 36df240cea04990e8c18aa0b90bd63374f22dbd3 (diff) | |
| download | openocd+libswd-b48a94f05da3a887f1978da01db77b79513d4aa9.tar.gz openocd+libswd-b48a94f05da3a887f1978da01db77b79513d4aa9.tar.bz2 openocd+libswd-b48a94f05da3a887f1978da01db77b79513d4aa9.tar.xz openocd+libswd-b48a94f05da3a887f1978da01db77b79513d4aa9.zip | |
MIPS: remove unused arg from mips_ejtag_set_instr
This arg was never used and was just taken from the arm jtag code.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Diffstat (limited to 'src/target/mips_m4k.c')
| -rw-r--r-- | src/target/mips_m4k.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index d1b45891..5919f5b9 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -113,7 +113,7 @@ int mips_m4k_poll(struct target *target) /* read ejtag control reg */ jtag_set_end_state(TAP_IDLE); - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* clear this bit before handling polling @@ -125,7 +125,7 @@ int mips_m4k_poll(struct target *target) jtag_set_end_state(TAP_IDLE); ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); LOG_DEBUG("Reset Detected"); } @@ -136,7 +136,7 @@ int mips_m4k_poll(struct target *target) if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { jtag_set_end_state(TAP_IDLE); - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); target->state = TARGET_HALTED; @@ -228,12 +228,12 @@ int mips_m4k_assert_reset(struct target *target) { /* use hardware to catch reset */ jtag_set_end_state(TAP_IDLE); - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); } else { jtag_set_end_state(TAP_IDLE); - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); } if (assert_srst) @@ -257,21 +257,21 @@ int mips_m4k_assert_reset(struct target *target) LOG_DEBUG("Using MTAP reset to reset processor..."); /* use microchip specific MTAP reset */ - mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL); - mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL); + mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP); + mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND); mchip_cmd = MCHP_ASERT_RST; mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); mchip_cmd = MCHP_DE_ASSERT_RST; mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); - mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL); + mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); } else { /* use ejtag reset - not supported by all cores */ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); } } @@ -933,7 +933,7 @@ int mips_m4k_examine(struct target *target) { /* we are using a pic32mx so select ejtag port * as it is not selected by default */ - mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL); + mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); LOG_DEBUG("PIC32MX Detected - using EJTAG Interface"); mips_m4k->is_pic32mx = true; } |