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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
| commit | c0787b699496080d48174713a0b30e81ef5db3be (patch) | |
| tree | 9dab9d70f9d87a6505592ae5484dfe0686d3ccbe /src/target/mips_m4k.c | |
| parent | 368daf44ff6aecb522952872a44bcf9e26b836f3 (diff) | |
| download | openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.gz openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.bz2 openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.xz openocd+libswd-c0787b699496080d48174713a0b30e81ef5db3be.zip | |
- correct the register hi/lo read - wrong way round
- all the register now can be written to, including the special CP0 regs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/mips_m4k.c')
| -rw-r--r-- | src/target/mips_m4k.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 2a96833d..61098694 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -139,6 +139,21 @@ int mips_m4k_poll(target_t *target) mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + /* clear this bit before handling polling + * as after reset registers will read zero */ + if (ejtag_ctrl & EJTAG_CTRL_ROCC) + { + /* we have detected a reset, clear flag + * otherwise ejtag will not work */ + jtag_add_end_state(TAP_RTI); + ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; + + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + LOG_DEBUG("Reset Detected"); + } + + /* check for processor halted */ if (ejtag_ctrl & EJTAG_CTRL_BRKST) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) @@ -168,18 +183,6 @@ int mips_m4k_poll(target_t *target) target->state = TARGET_RUNNING; } - if (ejtag_ctrl & EJTAG_CTRL_ROCC) - { - /* we have detected a reset, clear flag - * otherwise ejtag will not work */ - jtag_add_end_state(TAP_RTI); - ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; - - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - LOG_DEBUG("Reset Detected"); - } - // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); return ERROR_OK; @@ -289,7 +292,6 @@ int mips_m4k_assert_reset(target_t *target) return retval; } - return ERROR_OK; } |