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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-14 06:26:53 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-14 06:26:53 +0000 |
| commit | 53c41935cd72687ffb7f6b408a824f8e40f82ee9 (patch) | |
| tree | 140166efa41e2d4fc8312ae6e20992e704156b40 /src/target/target/pxa270.cfg | |
| parent | f2047d47756005b64abbb3f7f58d90b2b019c2b7 (diff) | |
| download | openocd+libswd-53c41935cd72687ffb7f6b408a824f8e40f82ee9.tar.gz openocd+libswd-53c41935cd72687ffb7f6b408a824f8e40f82ee9.tar.bz2 openocd+libswd-53c41935cd72687ffb7f6b408a824f8e40f82ee9.tar.xz openocd+libswd-53c41935cd72687ffb7f6b408a824f8e40f82ee9.zip | |
moved out stuff that wasn't already moved from openocd.pdf to the target library.
git-svn-id: svn://svn.berlios.de/openocd/trunk@576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/target/pxa270.cfg')
| -rw-r--r-- | src/target/target/pxa270.cfg | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg new file mode 100644 index 00000000..5946e757 --- /dev/null +++ b/src/target/target/pxa270.cfg @@ -0,0 +1,22 @@ +#Marvell/Intel PXA270 Script
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 260
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+#use combined on interfaces or targets that can’t set TRST/SRST separately
+reset_config trst_and_srst separate
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+#target configuration
+daemon_startup reset
+target xscale little reset_halt 0 pxa27x
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+working_area 0 0x5c000000 0x10000 nobackup
+run_and_halt_time 0 30
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# works for P30 flash
+flash bank cfi 0x00000000 0x1000000 2 4 0
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