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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-03 13:29:29 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-03 13:29:29 +0000 |
commit | 75e69503b9ca22136e261f889058e003b4622286 (patch) | |
tree | fa54ba63bfdb0e7b3fe2cb386a30064754d45128 /src/target/target/zy1000.cfg | |
parent | fe20b12fbdfa4a8128b16852ca704c3b5a13c06c (diff) | |
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added at91sam9260.cfg, nslu2.cfg, pxa255.cfg, pxa255_sst.cfg
zy1000.cfg
git-svn-id: svn://svn.berlios.de/openocd/trunk@435 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/target/zy1000.cfg')
-rw-r--r-- | src/target/target/zy1000.cfg | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg new file mode 100644 index 00000000..e6929f22 --- /dev/null +++ b/src/target/target/zy1000.cfg @@ -0,0 +1,30 @@ +#Script for ZY1000
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#target configuration
+#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
+target arm7tdmi little reset_init 0 arm7tdmi-s_r4
+
+# at CPU CLK <32kHz this must be disabled
+arm7 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+
+flash bank ecosflash 0x01000000 0x200000 2 2 0 /rom/at91eb40a.elf
+target_script 0 reset event/zy1000_reset.script
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+working_area 0 0x00000000 0x20000 nobackup
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