diff options
| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-07 11:42:03 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-03-07 11:42:03 +0000 |
| commit | c9f1b34077aa169ff44791f2dc55dc897ee201bc (patch) | |
| tree | 5b2fe55d62175d6d1e9834364dac37ec87390633 /src/target/target | |
| parent | 189ef12a52d4730c56ff0f81aa5415eb74a7eb85 (diff) | |
| download | openocd+libswd-c9f1b34077aa169ff44791f2dc55dc897ee201bc.tar.gz openocd+libswd-c9f1b34077aa169ff44791f2dc55dc897ee201bc.tar.bz2 openocd+libswd-c9f1b34077aa169ff44791f2dc55dc897ee201bc.tar.xz openocd+libswd-c9f1b34077aa169ff44791f2dc55dc897ee201bc.zip | |
minor corrections for target scripts.
git-svn-id: svn://svn.berlios.de/openocd/trunk@468 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/target')
| -rw-r--r-- | src/target/target/pxa255.cfg | 77 | ||||
| -rw-r--r-- | src/target/target/pxa255_sst.cfg | 2 |
2 files changed, 2 insertions, 77 deletions
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg index 2a452135..0c4e6b9c 100644 --- a/src/target/target/pxa255.cfg +++ b/src/target/target/pxa255.cfg @@ -5,82 +5,7 @@ target xscale little reset_init 0 pxa255 reset_config trst_and_srst run_and_halt_time 0 30 -target_script 0 reset /ram/pxa255.init +target_script 0 reset event/pxa255_reset.script #xscale debug_handler 0 0xFFFF0800 # debug handler base address -trunc /ram/pxa255.init -append /ram/pxa255.init #configuration file for PXA250 Evaluation Board -append /ram/pxa255.init # ----------------------------------------------------- -append /ram/pxa255.init # -append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access -append /ram/pxa255.init # -append /ram/pxa255.init # setup GPIO -append /ram/pxa255.init # -append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init -append /ram/pxa255.init -append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init -append /ram/pxa255.init # -append /ram/pxa255.init # setup memory controller -append /ram/pxa255.init # -append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1 -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init # -append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init -append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS -append /ram/pxa255.init sleep 20 -append /ram/pxa255.init diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg index a5fea173..01d63e41 100644 --- a/src/target/target/pxa255_sst.cfg +++ b/src/target/target/pxa255_sst.cfg @@ -7,7 +7,7 @@ # RAM at 0x40000000 # Flash at 0x00000000 # -script /target/pxa255.cfg +script target/pxa255.cfg # flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options] flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe working_area 0 0x4000000 0x4000 nobackup 0 |