- jtag_khz/speed are now single parameter only. These are used

from pre/post_reset event scripts. Adding the second parameter was
a mistake seen in retrospect. this gives precise control in post_reset
for *when* the post reset speed is set. The pre_reset event was
added *after* the second parameter to jtag_khz/speed
- the target implementations no longer gets involved in the reset mode
scheme. Either they reset a target into a halted mode or not.
target_process_reset()
detects if the reset halt failed or not.
- tcl target event names are now target_N_name.  Mainly internal
at this early stage, but best to get the naming right now.
- added hardcoded reset modes from gdb_server.c. I don't know precisely what
these defaults should be or if it should be made configurable. Perhaps some
hardcoded defaults will do for now and it can be made configurable later.
- bugfix in cortex_m3.c for reset_run_and_xxx?
- issue syntax error upon obsolete argument in target command instead of
printing message that will surely drown in the log

git-svn-id: svn://svn.berlios.de/openocd/trunk@849 b42882b7-edfa-0310-969c-e2dbd0fdcd60

5 files changed, 47 insertions, 11 deletions

diff --git a/src/target/target/str710.cfg b/src/target/target/str710.cfg
index 32589cc1..8eb8775d 100644
--- a/src/target/target/str710.cfg
+++ b/src/target/target/str710.cfg
@@ -1,5 +1,11 @@
 #start slow, speed up after reset
-jtag_khz 10, 6000
+jtag_khz 10
+proc target_0_pre_reset {} {
+	jtag_khz 10
+}
+proc target_0_post_reset {} {
+	jtag_khz 6000
+}
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst srst_pulls_trst
@@ -15,6 +21,7 @@ run_and_halt_time 0 30
 
 target_script 0 gdb_program_config event/str710_program.script
 
+
 working_area 0 0x2000C000 0x4000 nobackup
 
 #flash bank str7x <base> <size> 0 0 <target#> <variant>
diff --git a/src/target/target/str730.cfg b/src/target/target/str730.cfg
index 61270481..77f86a7c 100644
--- a/src/target/target/str730.cfg
+++ b/src/target/target/str730.cfg
@@ -1,6 +1,14 @@
 #STR730 CPU
 
-jtag_khz 10, 3000
+
+jtag_khz 3000
+proc target_0_pre_reset {} {
+	jtag_khz 10
+}
+proc target_0_post_reset {} {
+	jtag_khz 3000
+}
+
 
 #use combined on interfaces or targets that can’t set TRST/SRST separately
 #reset_config trst_and_srst srst_pulls_trst
diff --git a/src/target/target/str750.cfg b/src/target/target/str750.cfg
index 35509f46..d00eae09 100644
--- a/src/target/target/str750.cfg
+++ b/src/target/target/str750.cfg
@@ -1,7 +1,13 @@
 #STR750 CPU
 
 # jtag speed
-jtag_khz 10, 3000
+jtag_khz 10
+proc target_0_pre_reset {} {
+	jtag_khz 10
+}
+proc target_0_post_reset {} {
+	jtag_khz 3000
+}
 
 #use combined on interfaces or targets that can’t set TRST/SRST separately
 #reset_config trst_and_srst srst_pulls_trst
@@ -15,9 +21,6 @@ jtag_device 4 0x1 0xf 0xe
 jtag_nsrst_delay 500
 jtag_ntrst_delay 500
 
-#target configuration
-daemon_startup reset
-
 #target <type> <startup mode>
 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
 target arm7tdmi little 0 arm7tdmi
diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
index bce03d8d..14bb4973 100644
--- a/src/target/target/str912.cfg
+++ b/src/target/target/str912.cfg
@@ -1,7 +1,26 @@
 # script for str9
 
-# jtag speed
-jtag_khz 16 3000
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+
+jtag_khz 16
+proc target_0_pre_reset {} {
+	jtag_khz 16
+}
+
+proc target_0_post_reset {} {
+	# We can increase speed now that we know the target is halted.
+	jtag_khz 3000
+	
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191 
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+	
+	
+}
+
 
 jtag_nsrst_delay 100
 jtag_ntrst_delay 100
@@ -20,7 +39,6 @@ jtag_device 5 0x1 0x1 0x1e
 target arm966e little 1 arm966e
 run_and_halt_time 0 30
 
-target_script 0 reset event/str912_reset.script
 
 working_area 0 0x50000000 16384 nobackup
 
diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg
index 26d56814..86848844 100644
--- a/src/target/target/zy1000.cfg
+++ b/src/target/target/zy1000.cfg
@@ -17,9 +17,9 @@ jtag_device 4 0x1 0xf 0xe
 target arm7tdmi little 0 arm7tdmi-s_r4
 
 # at CPU CLK <32kHz this must be disabled
-arm7 fast_memory_access enable
+arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
-
+arm7_9 sw_bkpts enable
 
 flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
 target_script 0 reset event/zy1000_reset.script