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| author | Luca Ellero <lroluk@gmail.com> | 2011-02-09 20:36:14 +0000 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-02-10 10:07:56 +0100 |
| commit | 05ab8bdb813acdcd74afa71d6656c2df816cb230 (patch) | |
| tree | 76062d8e3da6d429ff6918afdd94582515d0883e /src/target/xscale.c | |
| parent | 94e90cbf16cb14c997e68b780b1c4397f2cc2257 (diff) | |
| download | openocd+libswd-05ab8bdb813acdcd74afa71d6656c2df816cb230.tar.gz openocd+libswd-05ab8bdb813acdcd74afa71d6656c2df816cb230.tar.bz2 openocd+libswd-05ab8bdb813acdcd74afa71d6656c2df816cb230.tar.xz openocd+libswd-05ab8bdb813acdcd74afa71d6656c2df816cb230.zip | |
cortex_a9: implement read/write memory through APB-AP
This patch adds read/write capability to memory addresses not
accessible through AHB-AP (for example "boot ROM code").
To select AHB or APB, a "dap apsel" command must be issued:
dap apsel 0 -> following memory accesses are through AHB
dap apsel 1 -> following memory accesses are through APB
NOTE: at the moment APB memory accesses are very slow, compared
to AHB accesses. Work has to be done to get it faster (for
example LDR/STR instead od LDRB/STRB)
Signed-off-by: Luca Ellero <lroluk@gmail.com>
Diffstat (limited to 'src/target/xscale.c')
0 files changed, 0 insertions, 0 deletions