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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-07 14:55:08 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-07 14:57:44 -0800 |
| commit | 19ad7f828ba36f398f52749c2f33e25a3ea78ac2 (patch) | |
| tree | 141e7c3e273efec584b7af3df91d08628e31f785 /src/target/xscale.c | |
| parent | 927ae6899df12e4667d181575cc0494bf12ff209 (diff) | |
| download | openocd+libswd-19ad7f828ba36f398f52749c2f33e25a3ea78ac2.tar.gz openocd+libswd-19ad7f828ba36f398f52749c2f33e25a3ea78ac2.tar.bz2 openocd+libswd-19ad7f828ba36f398f52749c2f33e25a3ea78ac2.tar.xz openocd+libswd-19ad7f828ba36f398f52749c2f33e25a3ea78ac2.zip | |
ARM: don't clone arm_arch_state() code
Have various ARM cores delegate to arm_arch_state() to display
basic information, instead of duplicating that logic.
This shrinks the code, makes them all report when semihosting
is active, and highlights which data are specific to this core.
(Like ARM720 not having separate instruction and data caches.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/xscale.c')
| -rw-r--r-- | src/target/xscale.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/target/xscale.c b/src/target/xscale.c index 61994dcb..ac697da9 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -865,15 +865,8 @@ static int xscale_arch_state(struct target *target) return ERROR_INVALID_ARGUMENTS; } - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s" - "%s", - arm_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s", state[xscale->armv4_5_mmu.mmu_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled], |