- remove target specific variant and use target->variant member

- fix build warning in cortex_m3
- code cleanup - remove trailing lf and convert c++ comments

git-svn-id: svn://svn.berlios.de/openocd/trunk@1238 b42882b7-edfa-0310-969c-e2dbd0fdcd60

37 files changed, 171 insertions, 378 deletions

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index d4eb6bd5..12c20943 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -447,21 +447,19 @@ int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
 	arm7tdmi_init_target(cmd_ctx, target);
 
 	return ERROR_OK;
-
 }
 
 int arm720t_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
+int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 {
 	arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 
-	arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
+	arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 
 	arm7tdmi->arch_info = arm720t;
 	arm720t->common_magic = ARM720T_COMMON_MAGIC;
@@ -485,7 +483,7 @@ int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 
-	arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
+	arm720t_init_arch_info(target, arm720t, target->tap);
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 357daa39..cdf46a08 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -66,7 +66,6 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
-
 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
 {
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -143,7 +142,6 @@ int arm7_9_setup(target_t *target)
 	return arm7_9_clear_watchpoints(arm7_9);
 }
 
-
 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -269,7 +267,6 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	}
 
 	return retval;
-
 }
 
 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
@@ -388,7 +385,6 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		}
 	}
 
-
 	arm7_9->breakpoint_count++;
 
 	return arm7_9_set_breakpoint(target, breakpoint);
@@ -571,9 +567,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-
-
-
 int arm7_9_execute_sys_speed(struct target_s *target)
 {
 	int retval;
@@ -642,9 +635,9 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 		/* check for DBGACK and SYSCOMP set (others don't care) */
 
 		/* NB! These are constants that must be available until after next jtag_execute() and
-		   we evaluate the values upon first execution in lieu of setting up these constants
-		   during early setup.
-		*/
+		 * we evaluate the values upon first execution in lieu of setting up these constants
+		 * during early setup.
+		 * */
 		buf_set_u32(check_value, 0, 32, 0x9);
 		buf_set_u32(check_mask, 0, 32, 0x9);
 		set=1;
@@ -689,7 +682,6 @@ int arm7_9_handle_target_request(void *priv)
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 
-
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
 
@@ -857,28 +849,25 @@ int arm7_9_assert_reset(target_t *target)
 		jtag_add_reset(0, 1);
 	}
 
-
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
 	armv4_5_invalidate_core_regs(target);
 
-    if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+	if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
 	{
 		/* debug entry was already prepared in arm7_9_assert_reset() */
 		target->debug_reason = DBG_REASON_DBGRQ;
 	}
 
 	return ERROR_OK;
-
 }
 
 int arm7_9_deassert_reset(target_t *target)
 {
 	int retval=ERROR_OK;
 	LOG_DEBUG("target->state: %s",
-		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
-
+		Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
 
 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
@@ -1527,7 +1516,6 @@ void arm7_9_enable_breakpoints(struct target_s *target)
 	}
 }
 
-
 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1833,7 +1821,6 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 		}
 
 	return err;
-
 }
 
 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
@@ -1900,7 +1887,6 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 	}
 
 	return ERROR_OK;
-
 }
 
 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
@@ -2326,7 +2312,6 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 static int dcc_count;
 static u8 *dcc_buffer;
 
-
 static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
 {
 	int retval = ERROR_OK;
@@ -2342,8 +2327,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
 	if (count>2)
 	{
 		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
-		   core function repeated.
-		 */
+		 * core function repeated. */
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
 		buffer+=4;
 
@@ -2373,7 +2357,6 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
 	return target_wait_state(target, TARGET_HALTED, 500);
 }
 
-
 static const u32 dcc_code[] =
 {
 	/* MRC      TST         BNE         MRC         STR         B */
@@ -2382,7 +2365,6 @@ static const u32 dcc_code[] =
 
 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
 
-
 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 {
 	int retval;
@@ -2429,8 +2411,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
 	buf_set_u32(reg_params[0].value, 0, 32, address);
 
-	//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
-	// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
 	dcc_count=count;
 	dcc_buffer=buffer;
 	retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
@@ -2741,10 +2721,8 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
 	value = strtoul(args[2], NULL, 0);
 
 	return arm7_9_write_core_reg(target, num, mode, value);
-
 }
 
-
 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index a975b5f3..3cf90511 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -154,5 +154,4 @@ int arm7_9_execute_sys_speed(struct target_s *target);
 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
 
-
 #endif /* ARM7_9_COMMON_H */
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index be98c8e1..41b4181a 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -364,7 +364,6 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 	 * reading PC in Thumb state gives address of instruction + 4
 	 */
 	*pc -= 0xa;
-
 }
 
 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
@@ -391,7 +390,6 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 			/* nothing fetched, STM still in EXECUTE (1+i cycle) */
 			arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 	}
-
 }
 
 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
@@ -435,7 +433,6 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 			}
 		}
 	}
-
 }
 
 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
@@ -456,7 +453,6 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	/* nothing fetched, STR still in EXECUTE (2nd cycle) */
 	arm7tdmi_clock_data_in(jtag_info, xpsr);
-
 }
 
 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
@@ -507,7 +503,6 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	/* nothing fetched, MSR in EXECUTE (2) */
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
 }
 
 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
@@ -535,7 +530,6 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 			arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 	}
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
-
 }
 
 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
@@ -549,7 +543,6 @@ void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
-
 }
 
 void arm7tdmi_load_hword_reg(target_t *target, int num)
@@ -563,7 +556,6 @@ void arm7tdmi_load_hword_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_load_byte_reg(target_t *target, int num)
@@ -577,7 +569,6 @@ void arm7tdmi_load_byte_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
@@ -591,7 +582,6 @@ void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
-
 }
 
 void arm7tdmi_store_hword_reg(target_t *target, int num)
@@ -605,7 +595,6 @@ void arm7tdmi_store_hword_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_store_byte_reg(target_t *target, int num)
@@ -619,7 +608,6 @@ void arm7tdmi_store_byte_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
-
 }
 
 void arm7tdmi_write_pc(target_t *target, u32 pc)
@@ -658,7 +646,6 @@ void arm7tdmi_branch_resume(target_t *target)
 
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
-
 }
 
 void arm7tdmi_branch_resume_thumb(target_t *target)
@@ -720,7 +707,6 @@ void arm7tdmi_branch_resume_thumb(target_t *target)
 
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
-
 }
 
 void arm7tdmi_build_reg_cache(target_t *target)
@@ -771,20 +757,17 @@ int arm7tdmi_examine(struct target_s *target)
 
 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 {
-
 	arm7tdmi_build_reg_cache(target);
 
 	return ERROR_OK;
-
 }
 
 int arm7tdmi_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant)
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
 {
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -838,34 +821,21 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
 	arm7tdmi->arch_info = NULL;
 	arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 
-	if (variant)
-	{
-		arm7tdmi->variant = strdup(variant);
-	}
-	else
-	{
-		arm7tdmi->variant = strdup("");
-	}
-
 	arm7_9_init_arch_info(target, arm7_9);
 
 	return ERROR_OK;
 }
 
-
-
 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
 {
 	arm7tdmi_common_t *arm7tdmi;
 
 	arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
-
-	arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
+	arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
 
 	return ERROR_OK;
 }
 
-
 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 {
 	int retval;
@@ -873,5 +843,4 @@ int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 	retval = arm7_9_register_commands(cmd_ctx);
 
 	return retval;
-
 }
diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h
index ab078e28..3624af6e 100644
--- a/src/target/arm7tdmi.h
+++ b/src/target/arm7tdmi.h
@@ -35,15 +35,13 @@
 typedef struct arm7tdmi_common_s
 {
 	int common_magic;
-	char *variant;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm7tdmi_common_t;
 
 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant);
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap);
 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm7tdmi_examine(struct target_s *target);
 
-
 #endif /* ARM7TDMI_H */
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 2aed9966..5003445a 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -703,23 +703,21 @@ int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
 	arm9tdmi_init_target(cmd_ctx, target);
 
 	return ERROR_OK;
-
 }
 
 int arm920t_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant)
+int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
 	/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 	 */
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm920t;
 	arm920t->common_magic = ARM920T_COMMON_MAGIC;
@@ -752,7 +750,7 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
 
-	arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
+	arm920t_init_arch_info(target, arm920t, target->tap);
 
 	return ERROR_OK;
 }
@@ -995,10 +993,8 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 				 i_cache[segment][index].data[i] = regs[i];
 				 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 			}
-
 		}
 
-
 		/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 		regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 		arm9tdmi_write_core_regs(target, 0x1, regs);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c959f135..ee8bcbc9 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -98,7 +98,6 @@ target_type_t arm926ejs_target =
 	.mmu = arm926ejs_mmu
 };
 
-
 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 {
 	/* The ARM926EJ-S' instruction register is 4 bits wide */
@@ -498,7 +497,6 @@ void arm926ejs_post_debug_entry(target_t *target)
 	LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
-
 	u32 cache_dbg_ctrl;
 
 	/* read-modify-write CP15 cache debug control register
@@ -666,7 +664,6 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
 }
 
 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -705,23 +702,21 @@ int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
 	arm9tdmi_init_target(cmd_ctx, target);
 
 	return ERROR_OK;
-
 }
 
 int arm926ejs_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
 	/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 	 */
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm926ejs;
 	arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
@@ -755,7 +750,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
 	return ERROR_OK;
 }
@@ -945,6 +940,7 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char
 
 	return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 }
+
 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 {
 	int retval;
diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h
index 1b280de7..17705557 100644
--- a/src/target/arm926ejs.h
+++ b/src/target/arm926ejs.h
@@ -43,7 +43,7 @@ typedef struct arm926ejs_common_s
 	u32 d_far;
 } arm926ejs_common_t;
 
-extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant);
+extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap);
 extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx); 
 extern int arm926ejs_arch_state(struct target_s *target); 
 extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); 
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index a7cee34f..50599fd1 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -98,16 +98,15 @@ int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
 
 int arm966e_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap, const char *variant)
+int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
-	arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm966e;
 	arm966e->common_magic = ARM966E_COMMON_MAGIC;
@@ -125,7 +124,7 @@ int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
 {
 	arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
 
-	arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
+	arm966e_init_arch_info(target, arm966e, target->tap);
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index f717dc9d..340c5beb 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -507,7 +507,6 @@ void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 			/* nothing fetched, STM in MEMORY (i'th cycle) */
 			arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 	}
-
 }
 
 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
@@ -549,7 +548,6 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 					break;
 			}
 	}
-
 }
 
 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
@@ -574,7 +572,6 @@ void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	/* nothing fetched, STR in MEMORY */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
-
 }
 
 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
@@ -664,7 +661,6 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 			arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 	}
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
 }
 
 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
@@ -677,7 +673,6 @@ void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 	/* put system-speed load-multiple into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_load_hword_reg(target_t *target, int num)
@@ -702,7 +697,6 @@ void arm9tdmi_load_byte_reg(target_t *target, int num)
 	/* put system-speed load byte into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
@@ -715,7 +709,6 @@ void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 	/* put system-speed store-multiple into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_hword_reg(target_t *target, int num)
@@ -728,7 +721,6 @@ void arm9tdmi_store_hword_reg(target_t *target, int num)
 	/* put system-speed store half-word into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_store_byte_reg(target_t *target, int num)
@@ -741,7 +733,6 @@ void arm9tdmi_store_byte_reg(target_t *target, int num)
 	/* put system-speed store byte into the pipeline */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_write_pc(target_t *target, u32 pc)
@@ -768,7 +759,6 @@ void arm9tdmi_write_pc(target_t *target, u32 pc)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
 }
 
 void arm9tdmi_branch_resume(target_t *target)
@@ -780,7 +770,6 @@ void arm9tdmi_branch_resume(target_t *target)
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-
 }
 
 void arm9tdmi_branch_resume_thumb(target_t *target)
@@ -841,7 +830,6 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-
 }
 
 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
@@ -888,7 +876,6 @@ void arm9tdmi_build_reg_cache(target_t *target)
 	armv4_5->core_cache = (*cache_p);
 }
 
-
 int arm9tdmi_examine(struct target_s *target)
 {
 	/* get pointers to arch-specific information */
@@ -932,16 +919,14 @@ int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
 	arm9tdmi_build_reg_cache(target);
 
 	return ERROR_OK;
-
 }
 
 int arm9tdmi_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant)
+int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
 {
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
@@ -995,15 +980,6 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_
 	arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 	arm9tdmi->arch_info = NULL;
 
-	if (variant)
-	{
-		arm9tdmi->variant = strdup(variant);
-	}
-	else
-	{
-		arm9tdmi->variant = strdup("");
-	}
-
 	arm7_9_init_arch_info(target, arm7_9);
 
 	/* override use of DBGRQ, this is safe on ARM9TDMI */
@@ -1045,13 +1021,11 @@ int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, a
 	return ERROR_OK;
 }
 
-
-
 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
 
-	arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
 
 	return ERROR_OK;
 }
@@ -1059,19 +1033,13 @@ int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
 {
 	int retval;
-
 	command_t *arm9tdmi_cmd;
-
-
+	
 	retval = arm7_9_register_commands(cmd_ctx);
-
 	arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
-
 	register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
-
-
+	
 	return retval;
-
 }
 
 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h
index 3cb3786b..fc650914 100644
--- a/src/target/arm9tdmi.h
+++ b/src/target/arm9tdmi.h
@@ -35,7 +35,6 @@
 typedef struct arm9tdmi_common_s
 {
 	int common_magic;
-	char *variant;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm9tdmi_common_t;
@@ -60,7 +59,7 @@ enum arm9tdmi_vector
 
 extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm9tdmi_examine(struct target_s *target);
-extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant);
+extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap);
 extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
 
 extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed);
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index bd9ea8e8..32daa792 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -178,7 +178,6 @@ reg_t armv4_5_gdb_dummy_fps_reg =
 	"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
 
-
 int armv4_5_get_core_reg(reg_t *reg)
 {
 	int retval;
@@ -663,7 +662,6 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 	return retval;
 }
 
-
 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 {
 	return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index b4ac0737..c2fde4a9 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -137,7 +137,6 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 	}
 };
 
-
 extern int armv4_5_arch_state(struct target_s *target);
 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 extern int armv4_5_invalidate_core_regs(target_t *target);
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index c73d1f9a..fd121f2f 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -238,8 +238,6 @@ static void watchpoint_free(target_t *target, watchpoint_t *watchpoint_remove)
 	free(watchpoint);
 }
 
-
-
 void watchpoint_remove(target_t *target, u32 address)
 {
 	watchpoint_t *watchpoint = target->watchpoints;
@@ -263,7 +261,6 @@ void watchpoint_remove(target_t *target, u32 address)
 	}
 }
 
-
 void watchpoint_clear_target(target_t *target)
 {
 	watchpoint_t *watchpoint;
diff --git a/src/target/breakpoints.h b/src/target/breakpoints.h
index 2ded1f02..9b60254b 100644
--- a/src/target/breakpoints.h
+++ b/src/target/breakpoints.h
@@ -69,4 +69,3 @@ extern void watchpoint_remove(struct target_s *target, u32 address);
 extern void watchpoint_clear_target(struct target_s *target);
 
 #endif /* BREAKPOINTS_H */
-
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index c0b579e5..a0832238 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -740,7 +740,7 @@ int cortex_m3_assert_reset(target_t *target)
 	 * when srst is asserted the luminary device seesm to also clear the debug registers
 	 * which does not match the armv7 debug TRM */
 		
-	if (strcmp(cortex_m3->variant, "lm3s") == 0)
+	if (strcmp(target->variant, "lm3s") == 0)
 	{
 		/* get revision of lm3s target, only early silicon has this issue
 		 * Fury Rev B, DustDevil Rev B, Tempest all ok */
@@ -1407,7 +1407,7 @@ int cortex_m3_examine(struct target_s *target)
 		/* Setup FPB */
 		target_read_u32(target, FP_CTRL, &fpcr);
 		cortex_m3->auto_bp_type = 1;
-		cortex_m3->fp_num_code = (fpcr >> 8) & 0x70 | (fpcr >> 4) & 0xF; /* bits [14:12] and [7:4] */
+		cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
 		cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
 		cortex_m3->fp_code_available = cortex_m3->fp_num_code;
 		cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
@@ -1517,7 +1517,7 @@ int cortex_m3_handle_target_request(void *priv)
 	return ERROR_OK;
 }
 
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
 {
 	armv7m_common_t *armv7m;
 	armv7m = &cortex_m3->armv7m;
@@ -1545,15 +1545,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
 	armv7m->pre_restore_context = NULL;
 	armv7m->post_restore_context = NULL;
 	
-	if (variant)
-	{
-		cortex_m3->variant = strdup(variant);
-	}
-	else
-	{
-		cortex_m3->variant = strdup("");
-	}
-	
 	armv7m_init_arch_info(target, armv7m);	
 	armv7m->arch_info = cortex_m3;
 	armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
@@ -1568,7 +1559,7 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
 	
-	cortex_m3_init_arch_info(target, cortex_m3, target->tap, target->variant);
+	cortex_m3_init_arch_info(target, cortex_m3, target->tap);
 	
 	return ERROR_OK;
 }
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index bce8dd89..9ef8f7a4 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -138,7 +138,6 @@ typedef struct cortex_m3_common_s
 {
 	int common_magic;
 	arm_jtag_t jtag_info;
-	char *variant;
 	
 	/* Context information */
 	u32 dcb_dhcsr;
@@ -190,6 +189,6 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 
 extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant);
+extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
 
 #endif /* CORTEX_M3_H */
diff --git a/src/target/cortex_swjdp.h b/src/target/cortex_swjdp.h
index 4fc8501e..6f997310 100644
--- a/src/target/cortex_swjdp.h
+++ b/src/target/cortex_swjdp.h
@@ -33,9 +33,9 @@
 #define DPAP_WRITE		0
 #define DPAP_READ		1
 #define DP_ZERO			0
-#define DP_CTRL_STAT    0x4
-#define DP_SELECT       0x8
-#define DP_RDBUFF       0xC
+#define DP_CTRL_STAT	0x4
+#define DP_SELECT		0x8
+#define DP_RDBUFF		0xC
 
 #define CORUNDETECT		(1<<0)
 #define SSTICKYORUN		(1<<1)
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index 9e7f47ca..f9ac2fd4 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -129,5 +129,4 @@ static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_add
 
 void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
 
-
 #endif /* EMBEDDED_ICE_H */
diff --git a/src/target/etb.h b/src/target/etb.h
index 260a0220..a41443b8 100644
--- a/src/target/etb.h
+++ b/src/target/etb.h
@@ -31,15 +31,15 @@
 /* ETB registers */
 enum
 {
-    ETB_ID = 0x00,
-    ETB_RAM_DEPTH = 0x01,
-    ETB_RAM_WIDTH = 0x02,
-    ETB_STATUS = 0x03,
-    ETB_RAM_DATA = 0x04,
-    ETB_RAM_READ_POINTER = 0x05,
-    ETB_RAM_WRITE_POINTER = 0x06,
-    ETB_TRIGGER_COUNTER = 0x07,
-    ETB_CTRL = 0x08,
+	ETB_ID = 0x00,
+	ETB_RAM_DEPTH = 0x01,
+	ETB_RAM_WIDTH = 0x02,
+	ETB_STATUS = 0x03,
+	ETB_RAM_DATA = 0x04,
+	ETB_RAM_READ_POINTER = 0x05,
+	ETB_RAM_WRITE_POINTER = 0x06,
+	ETB_TRIGGER_COUNTER = 0x07,
+	ETB_CTRL = 0x08,
 };
 
 typedef struct etb_s
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 92d2aa00..b0c4069e 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -645,7 +645,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 	arm7_9_common_t *arm7_9;
 	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
 	armv4_5 = target->arch_info;
 	arm7_9 = armv4_5->arch_info;
@@ -684,7 +684,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-
 int feroceon_examine(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5;
diff --git a/src/target/image.c b/src/target/image.c
index e7b7067d..fb4d8915 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -83,15 +83,15 @@ static int autodetect_image_type(image_t *image, char *url)
 		LOG_DEBUG("ELF image detected.");
 		image->type = IMAGE_ELF;
 	}
-	else if  ((buffer[0]==':') /* record start byte */
-	        &&(isxdigit(buffer[1]))
-	        &&(isxdigit(buffer[2]))
-	        &&(isxdigit(buffer[3]))
-	        &&(isxdigit(buffer[4]))
-	        &&(isxdigit(buffer[5]))
-	        &&(isxdigit(buffer[6]))
-	        &&(buffer[7]=='0') /* record type : 00 -> 05 */
-	        &&(buffer[8]>='0')&&(buffer[8]<'6'))
+	else if ((buffer[0]==':') /* record start byte */
+		&&(isxdigit(buffer[1]))
+		&&(isxdigit(buffer[2]))
+		&&(isxdigit(buffer[3]))
+		&&(isxdigit(buffer[4]))
+		&&(isxdigit(buffer[5]))
+		&&(isxdigit(buffer[6]))
+		&&(buffer[7]=='0') /* record type : 00 -> 05 */
+		&&(buffer[8]>='0')&&(buffer[8]<'6'))
 	{
 		LOG_DEBUG("IHEX image detected.");
 		image->type = IMAGE_IHEX;
@@ -381,7 +381,6 @@ int image_elf_read_headers(image_t *image)
 		return ERROR_IMAGE_FORMAT_ERROR;
 	}
 
-
 	elf->endianness = elf->header->e_ident[EI_DATA];
 	if ((elf->endianness!=ELFDATA2LSB)
 		 &&(elf->endianness!=ELFDATA2MSB))
@@ -1042,5 +1041,3 @@ int image_calculate_checksum(u8* buffer, u32 nbytes, u32* checksum)
 	*checksum = crc;
 	return ERROR_OK;
 }
-
-
diff --git a/src/target/image.h b/src/target/image.h
index 062a5467..c23cdf58 100644
--- a/src/target/image.h
+++ b/src/target/image.h
@@ -44,12 +44,12 @@
 
 typedef enum image_type
 {
-    IMAGE_BINARY,	/* plain binary */
-    IMAGE_IHEX,		/* intel hex-record format */
-    IMAGE_MEMORY,	/* target-memory pseudo-image */
-    IMAGE_ELF,		/* ELF binary */
-    IMAGE_SRECORD,	/* motorola s19 */
-    IMAGE_BUILDER,	/* when building a new image */
+	IMAGE_BINARY,	/* plain binary */
+	IMAGE_IHEX,		/* intel hex-record format */
+	IMAGE_MEMORY,	/* target-memory pseudo-image */
+	IMAGE_ELF,		/* ELF binary */
+	IMAGE_SRECORD,	/* motorola s19 */
+	IMAGE_BUILDER,	/* when building a new image */
 } image_type_t;
 
 typedef struct image_section_s
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 8a260a28..d5381233 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -320,7 +320,7 @@ reg_cache_t *mips32_build_reg_cache(target_t *target)
 	return cache;
 }
 
-int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant)
+int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap)
 {
 	target->arch_info = mips32;
 	mips32->common_magic = MIPS32_COMMON_MAGIC;
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 02f88b0a..646edb7d 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -119,7 +119,7 @@ typedef struct mips32_core_reg_s
 #define MIPS32_DRET					0x4200001F
 
 extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index 6440f948..ae95dd08 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -182,7 +182,7 @@ begin_ejtag_dma_read_b:
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
-	// Handle the bigendian/littleendian
+	/* Handle the bigendian/littleendian */
 	switch (addr & 0x3) {
 		case 0:
 			*data = v & 0xff;
diff --git a/src/target/mips32_dmaacc.h b/src/target/mips32_dmaacc.h
index 443fef80..2a57023f 100644
--- a/src/target/mips32_dmaacc.h
+++ b/src/target/mips32_dmaacc.h
@@ -27,10 +27,10 @@
 
 #include "mips_ejtag.h"
 
-#define EJTAG_CTRL_DMA_BYTE        0x00000000
-#define EJTAG_CTRL_DMA_HALFWORD    0x00000080
-#define EJTAG_CTRL_DMA_WORD        0x00000100
-#define EJTAG_CTRL_DMA_TRIPLEBYTE  0x00000180
+#define EJTAG_CTRL_DMA_BYTE			0x00000000
+#define EJTAG_CTRL_DMA_HALFWORD		0x00000080
+#define EJTAG_CTRL_DMA_WORD			0x00000100
+#define EJTAG_CTRL_DMA_TRIPLEBYTE	0x00000180
 
 #define RETRY_ATTEMPTS	0
 
@@ -45,9 +45,4 @@ extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int coun
 extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
 extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
 
-#if 0
-extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);
-extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);
-#endif
-
 #endif
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index 5cda497d..d452964c 100644
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -34,7 +34,7 @@
 #define UPPER16(u32) (u32 >> 16)
 #define LOWER16(u32) (u32 & 0xFFFF)
 #define NEG16(v) (((~(v)) + 1) & 0xFFFF)
-//#define NEG18(v) ( ((~(v)) + 1) & 0x3FFFF )
+/*#define NEG18(v) ( ((~(v)) + 1) & 0x3FFFF )*/
 
 extern int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
 extern int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 353126d9..7e7733e9 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -265,7 +265,6 @@ int mips_m4k_assert_reset(target_t *target)
 {
 	mips32_common_t *mips32 = target->arch_info;
 	mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-	mips_m4k_common_t *mips_m4k = mips32->arch_info;
 
 	LOG_DEBUG("target->state: %s",
 		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
@@ -288,7 +287,7 @@ int mips_m4k_assert_reset(target_t *target)
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 	}
 
-	if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
+	if (strcmp(target->variant, "ejtag_srst") == 0)
 	{
 		u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 		LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
@@ -735,23 +734,14 @@ int mips_m4k_quit(void)
 	return ERROR_OK;
 }
 
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
 {
 	mips32_common_t *mips32 = &mips_m4k->mips32_common;
 
-	if (variant)
-	{
-		mips_m4k->variant = strdup(variant);
-	}
-	else
-	{
-		mips_m4k->variant = strdup("");
-	}
-
 	mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 
 	/* initialize mips4k specific info */
-	mips32_init_arch_info(target, mips32, tap, variant);
+	mips32_init_arch_info(target, mips32, tap);
 	mips32->arch_info = mips_m4k;
 
 	return ERROR_OK;
@@ -761,7 +751,7 @@ int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 
-	mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
+	mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 
 	return ERROR_OK;
 }
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 4f5d3bff..ccc8e6e7 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,8 +32,6 @@ typedef struct mips_m4k_common_s
 {
 	int common_magic;
 	mips32_common_t mips32_common;
-	
-	char *variant;
 } mips_m4k_common_t;
 
 extern int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c
index 2b21e7fd..7c0f7ab0 100644
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -61,19 +61,19 @@ int oocd_trace_read_reg(oocd_trace_t *oocd_trace, int reg, u32 *value)
 
 int oocd_trace_write_reg(oocd_trace_t *oocd_trace, int reg, u32 value)
 {
-    size_t bytes_written;
-    u8 data[5];
+	size_t bytes_written;
+	u8 data[5];
 
-    data[0] = 0x18 | (reg & 0x7);
-    data[1] = value & 0xff;
-    data[2] = (value & 0xff00) >> 8;
-    data[3] = (value & 0xff0000) >> 16;
-    data[4] = (value & 0xff000000) >> 24;
+	data[0] = 0x18 | (reg & 0x7);
+	data[1] = value & 0xff;
+	data[2] = (value & 0xff00) >> 8;
+	data[3] = (value & 0xff0000) >> 16;
+	data[4] = (value & 0xff000000) >> 24;
 
-    bytes_written = write(oocd_trace->tty_fd, data, 5);
-    LOG_DEBUG("reg #%i: 0x%8.8x\n", reg, value);
+	bytes_written = write(oocd_trace->tty_fd, data, 5);
+	LOG_DEBUG("reg #%i: 0x%8.8x\n", reg, value);
 
-    return ERROR_OK;
+	return ERROR_OK;
 }
 
 int oocd_trace_read_memory(oocd_trace_t *oocd_trace, u8 *data, u32 address, u32 size)
@@ -143,7 +143,7 @@ int oocd_trace_init(etm_context_t *etm_ctx)
 	 * read up any leftover characters to ensure communication is in sync */
 	while ((bytes_read = read(oocd_trace->tty_fd, trash, sizeof(trash))) > 0)
 	{
-	    LOG_DEBUG("%i bytes read\n", bytes_read);
+		LOG_DEBUG("%i bytes read\n", bytes_read);
 	};
 	
 	return ERROR_OK;
@@ -190,8 +190,8 @@ int oocd_trace_read_trace(etm_context_t *etm_ctx)
 	u8 *trace_data;
 	int i;
 
-    oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status);
-    oocd_trace_read_reg(oocd_trace, OOCD_TRACE_ADDRESS, &address);
+	oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status);
+	oocd_trace_read_reg(oocd_trace, OOCD_TRACE_ADDRESS, &address);
 
 	/* check if we overflowed, and adjust first frame of the trace accordingly
 	 * if we didn't overflow, read only up to the frame that would be written next,
diff --git a/src/target/oocd_trace.h b/src/target/oocd_trace.h
index 77e985fb..9a655b60 100644
--- a/src/target/oocd_trace.h
+++ b/src/target/oocd_trace.h
@@ -30,12 +30,12 @@
 /* registers */
 enum
 {
-    OOCD_TRACE_ID = 0x7,
-    OOCD_TRACE_ADDRESS = 0x0,
-    OOCD_TRACE_TRIGGER_COUNTER = 0x01,
-    OOCD_TRACE_CONTROL = 0x2,
-    OOCD_TRACE_STATUS = 0x3,
-    OOCD_TRACE_SDRAM_COUNTER = 0x4,
+	OOCD_TRACE_ID = 0x7,
+	OOCD_TRACE_ADDRESS = 0x0,
+	OOCD_TRACE_TRIGGER_COUNTER = 0x01,
+	OOCD_TRACE_CONTROL = 0x2,
+	OOCD_TRACE_STATUS = 0x3,
+	OOCD_TRACE_SDRAM_COUNTER = 0x4,
 };
 
 /* commands */
diff --git a/src/target/register.c b/src/target/register.c
index 7d120ad2..37915eb4 100644
--- a/src/target/register.c
+++ b/src/target/register.c
@@ -107,8 +107,6 @@ reg_arch_type_t* register_get_arch_type(int id)
 	return NULL;
 }
 
-
-
 static int register_get_dummy_core_reg(reg_t *reg)
 {
 	return ERROR_OK;
diff --git a/src/target/register.h b/src/target/register.h
index 96bd3da9..60ac8e54 100644
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -70,4 +70,3 @@ extern reg_arch_type_t* register_get_arch_type(int id);
 extern void register_init_dummy(reg_t *reg);
 
 #endif /* REGISTER_H */
-
diff --git a/src/target/target.c b/src/target/target.c
index 560ee78c..c86ee8d4 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -61,7 +61,6 @@
 
 int cli_target_callback_event_handler(struct target_s *target, enum target_event event, void *priv);
 
-
 int handle_targets_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -90,8 +89,6 @@ static int jim_target( Jim_Interp *interp, int argc, Jim_Obj *const *argv);
 static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv);
 static int target_mem2array(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv);
 
-
-
 /* targets */
 extern target_type_t arm7tdmi_target;
 extern target_type_t arm720t_target;
@@ -166,18 +163,15 @@ const Jim_Nvp nvp_target_event[] = {
 	{ .value = TARGET_EVENT_OLD_gdb_program_config , .name = "old-gdb_program_config" },
 	{ .value = TARGET_EVENT_OLD_pre_resume         , .name = "old-pre_resume" },
 
-
 	{ .value = TARGET_EVENT_EARLY_HALTED, .name = "early-halted" },
 	{ .value = TARGET_EVENT_HALTED, .name = "halted" },
 	{ .value = TARGET_EVENT_RESUMED, .name = "resumed" },
 	{ .value = TARGET_EVENT_RESUME_START, .name = "resume-start" },
 	{ .value = TARGET_EVENT_RESUME_END, .name = "resume-end" },
 
-
 	{ .name = "gdb-start", .value = TARGET_EVENT_GDB_START },
 	{ .name = "gdb-end", .value = TARGET_EVENT_GDB_END },
 
-
 	/* historical name */
 
 	{ .value = TARGET_EVENT_RESET_START, .name = "reset-start" },
@@ -193,21 +187,15 @@ const Jim_Nvp nvp_target_event[] = {
 	{ .value = TARGET_EVENT_RESET_INIT , .name = "reset-init" },
 	{ .value = TARGET_EVENT_RESET_END, .name = "reset-end" },
 
-
-
-
-
 	{ .value = TARGET_EVENT_EXAMINE_START, .name = "examine-start" },
 	{ .value = TARGET_EVENT_EXAMINE_END, .name = "examine-end" },
 
-
 	{ .value = TARGET_EVENT_DEBUG_HALTED, .name = "debug-halted" },
 	{ .value = TARGET_EVENT_DEBUG_RESUMED, .name = "debug-resumed" },
 
 	{ .value = TARGET_EVENT_GDB_ATTACH, .name = "gdb-attach" },
 	{ .value = TARGET_EVENT_GDB_DETACH, .name = "gdb-detach" },
 
-
 	{ .value = TARGET_EVENT_GDB_FLASH_WRITE_START, .name = "gdb-flash-write-start" },
 	{ .value = TARGET_EVENT_GDB_FLASH_WRITE_END  , .name = "gdb-flash-write-end"   },
 
@@ -230,7 +218,6 @@ const Jim_Nvp nvp_target_state[] = {
 	{ .name = NULL, .value = -1 },
 };
 
-
 const Jim_Nvp nvp_target_debug_reason [] = {
 	{ .name = "debug-request"            , .value = DBG_REASON_DBGRQ },
 	{ .name = "breakpoint"               , .value = DBG_REASON_BREAKPOINT },
@@ -247,7 +234,7 @@ const Jim_Nvp nvp_target_endian[] = {
 	{ .name = "big",    .value = TARGET_BIG_ENDIAN },
 	{ .name = "little", .value = TARGET_LITTLE_ENDIAN },
 	{ .name = "be",     .value = TARGET_BIG_ENDIAN },
-        { .name = "le",     .value = TARGET_LITTLE_ENDIAN },
+	{ .name = "le",     .value = TARGET_LITTLE_ENDIAN },
 	{ .name = NULL,     .value = -1 },
 };
 
@@ -378,7 +365,6 @@ target_t* get_current_target(command_context_t *cmd_ctx)
 	return target;
 }
 
-
 int target_poll(struct target_s *target)
 {
 	/* We can't poll until after examine */
@@ -422,7 +408,6 @@ int target_resume(struct target_s *target, int current, u32 address, int handle_
 	return retval;
 }
 
-
 int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mode reset_mode)
 {
 	char buf[100];
@@ -448,7 +433,6 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
 	return retval;
 }
 
-
 static int default_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 {
 	*physical = virtual;
@@ -467,7 +451,6 @@ static int default_examine(struct target_s *target)
 	return ERROR_OK;
 }
 
-
 /* Targets that correctly implement init+examine, i.e.
  * no communication with target during init:
  *
@@ -563,7 +546,6 @@ int target_init(struct command_context_s *cmd_ctx)
 		target->type->run_algorithm_imp = target->type->run_algorithm;
 		target->type->run_algorithm = target_run_algorithm_imp;
 
-
 		if (target->type->mmu == NULL)
 		{
 			target->type->mmu = default_mmu;
@@ -709,7 +691,6 @@ int target_call_event_callbacks(target_t *target, enum target_event event)
 		target_call_event_callbacks(target, TARGET_EVENT_EARLY_HALTED);
 	}
 
-
 	LOG_DEBUG("target event %i (%s)",
 			  event,
 			  Jim_Nvp_value2name_simple( nvp_target_event, event )->name );
@@ -1051,7 +1032,6 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
 	return ERROR_OK;
 }
 
-
 /* Single aligned words are guaranteed to use 16 or 32 bit access
  * mode respectively, otherwise data is handled as quickly as
  * possible
@@ -1347,7 +1327,6 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
 	if((retval = trace_register_commands(cmd_ctx)) != ERROR_OK)
 		return retval;
 
-
 	return retval;
 }
 
@@ -1387,7 +1366,7 @@ int handle_targets_command(struct command_context_s *cmd_ctx, char *cmd, char **
 	}
 DumpTargets:
 
-  target = all_targets;
+	target = all_targets;
 	command_print(cmd_ctx, "    CmdName    Type       Endian     AbsChainPos Name          State     ");
 	command_print(cmd_ctx, "--  ---------- ---------- ---------- ----------- ------------- ----------");
 	while (target)
@@ -1407,8 +1386,7 @@ DumpTargets:
 	return ERROR_OK;
 }
 
-// every 300ms we check for reset & powerdropout and issue a "reset halt" if
-// so.
+/* every 300ms we check for reset & powerdropout and issue a "reset halt" if so. */
 
 static int powerDropout;
 static int srstAsserted;
@@ -1476,7 +1454,6 @@ static int sense_handler(void)
 	return ERROR_OK;
 }
 
-
 /* process target state changes */
 int handle_target(void *priv)
 {
@@ -1546,7 +1523,6 @@ int handle_target(void *priv)
 		target = target->next;
 	}
 
-
 	return retval;
 }
 
@@ -1661,7 +1637,6 @@ int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args
 	return ERROR_OK;
 }
 
-
 int handle_poll_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	int retval = ERROR_OK;
@@ -1694,7 +1669,6 @@ int handle_poll_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-
 	return retval;
 }
 
@@ -1739,14 +1713,14 @@ int target_wait_state(target_t *target, enum target_state state, int ms)
 		{
 			once=0;
 			LOG_DEBUG("waiting for target %s...",
-			      Jim_Nvp_value2name_simple(nvp_target_state,state)->name);
+				Jim_Nvp_value2name_simple(nvp_target_state,state)->name);
 		}
 
 		gettimeofday(&now, NULL);
 		if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec)))
 		{
 			LOG_ERROR("timed out while waiting for target %s",
-			      Jim_Nvp_value2name_simple(nvp_target_state,state)->name);
+				Jim_Nvp_value2name_simple(nvp_target_state,state)->name);
 			return ERROR_FAIL;
 		}
 	}
@@ -1858,7 +1832,6 @@ int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
 
 	address = strtoul(args[0], NULL, 0);
 
-
 	switch (cmd[2])
 	{
 		case 'w':
@@ -2025,7 +1998,6 @@ int handle_load_image_command(struct command_context_s *cmd_ctx, char *cmd, char
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-
 	duration_start_measure(&duration);
 
 	if (image_open(&image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
@@ -2053,7 +2025,6 @@ int handle_load_image_command(struct command_context_s *cmd_ctx, char *cmd, char
 		u32 offset=0;
 		u32 length=buf_cnt;
 
-
 		/* DANGER!!! beware of unsigned comparision here!!! */
 
 		if ((image.sections[i].base_address+buf_cnt>=min_address)&&
@@ -2470,6 +2441,7 @@ int handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args,
 	}
 	return retval;
 }
+
 static void writeLong(FILE *f, int l)
 {
 	int i;
@@ -2480,14 +2452,13 @@ static void writeLong(FILE *f, int l)
 	}
 
 }
+
 static void writeString(FILE *f, char *s)
 {
 	fwrite(s, 1, strlen(s), f);
 }
 
-
-
-// Dump a gmon.out histogram file.
+/* Dump a gmon.out histogram file. */
 static void writeGmon(u32 *samples, int sampleNum, char *filename)
 {
 	int i;
@@ -2495,14 +2466,14 @@ static void writeGmon(u32 *samples, int sampleNum, char *filename)
 	if (f==NULL)
 		return;
 	fwrite("gmon", 1, 4, f);
-	writeLong(f, 0x00000001); // Version
-	writeLong(f, 0); // padding
-	writeLong(f, 0); // padding
-	writeLong(f, 0); // padding
+	writeLong(f, 0x00000001); /* Version */
+	writeLong(f, 0); /* padding */
+	writeLong(f, 0); /* padding */
+	writeLong(f, 0); /* padding */
 
-	fwrite("", 1, 1, f);  // GMON_TAG_TIME_HIST
+	fwrite("", 1, 1, f);  /* GMON_TAG_TIME_HIST */
 
-	// figure out bucket size
+	/* figure out bucket size */
 	u32 min=samples[0];
 	u32 max=samples[0];
 	for (i=0; i<sampleNum; i++)
@@ -2519,7 +2490,7 @@ static void writeGmon(u32 *samples, int sampleNum, char *filename)
 
 	int addressSpace=(max-min+1);
 
-	static int const maxBuckets=256*1024; // maximum buckets.
+	static int const maxBuckets=256*1024; /* maximum buckets. */
 	int length=addressSpace;
 	if (length > maxBuckets)
 	{
@@ -2538,23 +2509,23 @@ static void writeGmon(u32 *samples, int sampleNum, char *filename)
 		long long a=address-min;
 		long long b=length-1;
 		long long c=addressSpace-1;
-		int index=(a*b)/c; // danger!!!! int32 overflows
+		int index=(a*b)/c; /* danger!!!! int32 overflows */
 		buckets[index]++;
 	}
 
-	//			   append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr))
-	writeLong(f, min); 					// low_pc
-	writeLong(f, max);		// high_pc
-	writeLong(f, length);		// # of samples
-	writeLong(f, 64000000); 			// 64MHz
+	/* append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr)) */
+	writeLong(f, min); 			/* low_pc */
+	writeLong(f, max);			/* high_pc */
+	writeLong(f, length);		/* # of samples */
+	writeLong(f, 64000000); 	/* 64MHz */
 	writeString(f, "seconds");
 	for (i=0; i<(15-strlen("seconds")); i++)
 	{
-		fwrite("", 1, 1, f);  // padding
+		fwrite("", 1, 1, f);	/* padding */
 	}
 	writeString(f, "s");
 
-//			   append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size)
+	/*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */
 
 	char *data=malloc(2*length);
 	if (data!=NULL)
@@ -2608,7 +2579,7 @@ int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd, char **
 
 	int numSamples=0;
 	int retval=ERROR_OK;
-	// hopefully it is safe to cache! We want to stop/restart as quickly as possible.
+	/* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */
 	reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
 
 	for (;;)
@@ -2620,10 +2591,10 @@ int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd, char **
 			samples[numSamples++]=t;
 			retval = target_resume(target, 1, 0, 0, 0); /* current pc, addr = 0, do not handle breakpoints, not debugging */
 			target_poll(target);
-			alive_sleep(10); // sleep 10ms, i.e. <100 samples/second.
+			alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
 		} else if (target->state == TARGET_RUNNING)
 		{
-			// We want to quickly sample the PC.
+			/* We want to quickly sample the PC. */
 			if((retval = target_halt(target)) != ERROR_OK)
 			{
 				free(samples);
@@ -2898,7 +2869,6 @@ static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	return target_array2mem( interp,target, argc, argv );
 }
 
-
 static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv)
 {
 	long l;
@@ -2983,7 +2953,6 @@ static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_
 		return JIM_ERR;
 	}
 
-
 	/* Transfer loop */
 
 	/* index counter */
@@ -3031,15 +3000,13 @@ static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_
 	return JIM_OK;
 }
 
-void
-target_all_handle_event( enum target_event e )
+void target_all_handle_event( enum target_event e )
 {
 	target_t *target;
 
-
 	LOG_DEBUG( "**all*targets: event: %d, %s",
-		   e,
-		   Jim_Nvp_value2name_simple( nvp_target_event, e )->name );
+			e,
+			Jim_Nvp_value2name_simple( nvp_target_event, e )->name );
 
 	target = all_targets;
 	while (target){
@@ -3048,8 +3015,7 @@ target_all_handle_event( enum target_event e )
 	}
 }
 
-void
-target_handle_event( target_t *target, enum target_event e )
+void target_handle_event( target_t *target, enum target_event e )
 {
 	target_event_action_t *teap;
 	int done;
@@ -3093,7 +3059,6 @@ enum target_cfg_param {
 	TCFG_CHAIN_POSITION,
 };
 
-
 static Jim_Nvp nvp_config_opts[] = {
 	{ .name = "-type",             .value = TCFG_TYPE },
 	{ .name = "-event",            .value = TCFG_EVENT },
@@ -3108,10 +3073,7 @@ static Jim_Nvp nvp_config_opts[] = {
 	{ .name = NULL, .value = -1 }
 };
 
-
-static int
-target_configure( Jim_GetOptInfo *goi,
-				  target_t *target )
+static int target_configure( Jim_GetOptInfo *goi, target_t *target )
 {
 	Jim_Nvp *n;
 	Jim_Obj *o;
@@ -3119,11 +3081,10 @@ target_configure( Jim_GetOptInfo *goi,
 	char *cp;
 	int e;
 
-
 	/* parse config or cget options ... */
 	while( goi->argc > 0 ){
 		Jim_SetEmptyResult( goi->interp );
-		//Jim_GetOpt_Debug( goi );
+		/* Jim_GetOpt_Debug( goi ); */
 
 		if( target->type->target_jim_configure ){
 			/* target defines a configure function */
@@ -3184,7 +3145,6 @@ target_configure( Jim_GetOptInfo *goi,
 				}
 			}
 
-
 			{
 				target_event_action_t *teap;
 
@@ -3377,12 +3337,8 @@ target_configure( Jim_GetOptInfo *goi,
 	return JIM_OK;
 }
 
-
 /** this is the 'tcl' handler for the target specific command */
-static int
-tcl_target_func( Jim_Interp *interp,
-				 int argc,
-				 Jim_Obj *const *argv )
+static int tcl_target_func( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
 {
 	Jim_GetOptInfo goi;
 	jim_wide a,b,c;
@@ -3393,7 +3349,6 @@ tcl_target_func( Jim_Interp *interp,
 	struct command_context_s *cmd_ctx;
 	int e;
 
-
 	enum {
 		TS_CMD_CONFIGURE,
 		TS_CMD_CGET,
@@ -3436,7 +3391,6 @@ tcl_target_func( Jim_Interp *interp,
 		{ .name = NULL, .value = -1 },
 	};
 
-
 	/* go past the "command" */
 	Jim_GetOpt_Setup( &goi, interp, argc-1, argv+1 );
 
@@ -3449,7 +3403,7 @@ tcl_target_func( Jim_Interp *interp,
 		Jim_GetOpt_NvpUnknown( &goi, target_options, 0 );
 		return e;
 	}
-	// Assume blank result
+	/* Assume blank result */
 	Jim_SetEmptyResult( goi.interp );
 
 	switch( n->value ){
@@ -3680,17 +3634,17 @@ tcl_target_func( Jim_Interp *interp,
 			Jim_GetOpt_NvpUnknown( &goi, nvp_assert, 1 );
 			return e;
 		}
-		// the halt or not param
+		/* the halt or not param */
 		e = Jim_GetOpt_Wide( &goi, &a);
 		if( e != JIM_OK ){
 			return e;
 		}
-		// determine if we should halt or not.
+		/* determine if we should halt or not. */
 		target->reset_halt = !!a;
-		// When this happens - all workareas are invalid.
+		/* When this happens - all workareas are invalid. */
 		target_free_all_working_areas_restore(target, 0);
 
-		// do the assert
+		/* do the assert */
 		if( n->value == NVP_ASSERT ){
 			target->type->assert_reset( target );
 		} else {
@@ -3705,7 +3659,7 @@ tcl_target_func( Jim_Interp *interp,
 		target->type->halt( target );
 		return JIM_OK;
 	case TS_CMD_WAITSTATE:
-		// params:  <name>  statename timeoutmsecs
+		/* params:  <name>  statename timeoutmsecs */
 		if( goi.argc != 2 ){
 			Jim_SetResult_sprintf( goi.interp, "%s STATENAME TIMEOUTMSECS", n->name );
 			return JIM_ERR;
@@ -3725,7 +3679,7 @@ tcl_target_func( Jim_Interp *interp,
 								   "target: %s wait %s fails (%d) %s",
 								   target->cmd_name,
 								   n->name,
-					       e, target_strerror_safe(e) );
+								   e, target_strerror_safe(e) );
 			return JIM_ERR;
 		} else {
 			return JIM_OK;
@@ -3776,11 +3730,8 @@ tcl_target_func( Jim_Interp *interp,
 	return JIM_ERR;
 }
 
-
-static int
-target_create( Jim_GetOptInfo *goi )
+static int target_create( Jim_GetOptInfo *goi )
 {
-
 	Jim_Obj *new_cmd;
 	Jim_Cmd *cmd;
 	const char *cp;
@@ -3834,7 +3785,6 @@ target_create( Jim_GetOptInfo *goi )
 		return JIM_ERR;
 	}
 
-
 	/* Create it */
 	target = calloc(1,sizeof(target_t));
 	/* set target number */
@@ -3892,6 +3842,10 @@ target_create( Jim_GetOptInfo *goi )
 		target->endianness = TARGET_LITTLE_ENDIAN;
 	}
 
+	/* incase variant is not set */
+	if (!target->variant)
+		target->variant = strdup("");
+	
 	/* create the target specific commands */
 	if( target->type->register_commands ){
 		(*(target->type->register_commands))( cmd_ctx );
@@ -3924,8 +3878,7 @@ target_create( Jim_GetOptInfo *goi )
 	return e;
 }
 
-static int
-jim_target( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
+static int jim_target( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
 {
 	int x,r,e;
 	jim_wide w;
@@ -3944,7 +3897,7 @@ jim_target( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
 	const char *target_cmds[] = {
 		"create", "types", "names", "current", "number",
 		"count",
-		NULL // terminate
+		NULL /* terminate */
 	};
 
 	LOG_DEBUG("Target command params:");
@@ -3959,7 +3912,7 @@ jim_target( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
 		return JIM_ERR;
 	}
 
-	//Jim_GetOpt_Debug( &goi );
+	/* Jim_GetOpt_Debug( &goi ); */
 	r = Jim_GetOpt_Enum( &goi, target_cmds, &x   );
 	if( r != JIM_OK ){
 		return r;
diff --git a/src/target/target.h b/src/target/target.h
index cbd3e2b2..500a5519 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -40,15 +40,15 @@
 struct reg_s;
 struct command_context_s;
 /*
-TARGET_UNKNOWN = 0: we don't know anything about the target yet
-TARGET_RUNNING = 1: the target is executing user code
-TARGET_HALTED  = 2: the target is not executing code, and ready to talk to the
-debugger. on an xscale it means that the debug handler is executing
-TARGET_RESET   = 3: the target is being held in reset (only a temporary state,
-not sure how this is used with all the recent changes)
-TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
-behalf of the debugger (e.g. algorithm for flashing)
-*/
+ * TARGET_UNKNOWN = 0: we don't know anything about the target yet
+ * TARGET_RUNNING = 1: the target is executing user code
+ * TARGET_HALTED  = 2: the target is not executing code, and ready to talk to the
+ * debugger. on an xscale it means that the debug handler is executing
+ * TARGET_RESET   = 3: the target is being held in reset (only a temporary state,
+ * not sure how this is used with all the recent changes)
+ * TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
+ * behalf of the debugger (e.g. algorithm for flashing) */
+
 enum target_state
 {
 	TARGET_UNKNOWN = 0,
@@ -228,7 +228,7 @@ typedef struct target_type_s
 	 *
 	 * It is illegal to talk to the target at this stage as this fn is invoked
 	 * before the JTAG chain has been examined/verified
-     */
+	 * */
 	int (*init_target)(struct command_context_s *cmd_ctx, struct target_s *target);
 	int (*quit)(void);
 
@@ -237,21 +237,21 @@ typedef struct target_type_s
 
 } target_type_t;
 
-// forward decloration
+/* forward decloration */
 typedef struct target_event_action_s target_event_action_t;
 
 typedef struct target_s
 {
 	target_type_t *type;				/* target type definition (name, access functions) */
-	const char *cmd_name;               /* tcl Name of target */
-	int target_number;                  /* generaly, target index but may not be in order */
-	jtag_tap_t *tap;                 /* where on the jtag chain is this */
-	const char *variant;                /* what varient of this chip is it? */
+	const char *cmd_name;				/* tcl Name of target */
+	int target_number;					/* generaly, target index but may not be in order */
+	jtag_tap_t *tap;					/* where on the jtag chain is this */
+	const char *variant;				/* what varient of this chip is it? */
 	target_event_action_t *event_action;
 
 	int reset_halt;						/* attempt resetting the CPU into the halted mode? */
 	u32 working_area;					/* working area (initialized RAM). Evaluated
-										   upon first allocation from virtual/physical address. */
+										 * upon first allocation from virtual/physical address. */
 	u32 working_area_virt;				/* virtual address */
 	u32 working_area_phys;				/* physical address */
 	u32 working_area_size;				/* size in bytes */
@@ -269,27 +269,27 @@ typedef struct target_s
 	void *arch_info;					/* architecture specific information */
 	struct target_s *next;				/* next target in list */
 
-	int display; 						/* display async info in telnet session. Do not display
-										   lots of halted/resumed info when stepping in debugger. */
+	int display;						/* display async info in telnet session. Do not display
+										 * lots of halted/resumed info when stepping in debugger. */
 } target_t;
 
 enum target_event
 {
-	// OLD historical names
-	//  - Prior to the great TCL change
-	//  - June/July/Aug 2008
-	//  - Duane Ellis
+	/* LD historical names
+	 * - Prior to the great TCL change
+	 * - June/July/Aug 2008
+	 * - Duane Ellis */
 	TARGET_EVENT_OLD_gdb_program_config,
 	TARGET_EVENT_OLD_pre_reset,
 	TARGET_EVENT_OLD_post_reset,
 	TARGET_EVENT_OLD_pre_resume,
 
 	/* allow GDB to do stuff before others handle the halted event,
- 	this is in lieu of defining ordering of invocation of events,
- 	which would be more complicated */
- 	TARGET_EVENT_EARLY_HALTED,
- 	TARGET_EVENT_HALTED,		/* target entered debug state from normal execution or reset */
- 	TARGET_EVENT_RESUMED,		/* target resumed to normal execution */
+	 * this is in lieu of defining ordering of invocation of events,
+	 * which would be more complicated */
+	TARGET_EVENT_EARLY_HALTED,
+	TARGET_EVENT_HALTED,		/* target entered debug state from normal execution or reset */
+	TARGET_EVENT_RESUMED,		/* target resumed to normal execution */
 	TARGET_EVENT_RESUME_START,
 	TARGET_EVENT_RESUME_END,
 
@@ -308,14 +308,12 @@ enum target_event
 	TARGET_EVENT_RESET_INIT,
 	TARGET_EVENT_RESET_END,
 
-
- 	TARGET_EVENT_DEBUG_HALTED,	/* target entered debug state, but was executing on behalf of the debugger */
- 	TARGET_EVENT_DEBUG_RESUMED, /* target resumed to execute on behalf of the debugger */
+	TARGET_EVENT_DEBUG_HALTED,	/* target entered debug state, but was executing on behalf of the debugger */
+	TARGET_EVENT_DEBUG_RESUMED, /* target resumed to execute on behalf of the debugger */
 
 	TARGET_EVENT_EXAMINE_START,
 	TARGET_EVENT_EXAMINE_END,
 
-
 	TARGET_EVENT_GDB_ATTACH,
 	TARGET_EVENT_GDB_DETACH,
 
@@ -330,7 +328,7 @@ extern const Jim_Nvp nvp_target_event[];
 struct target_event_action_s {
 	enum target_event event;
 	Jim_Obj *body;
-	int      has_percent;
+	int has_percent;
 	target_event_action_t *next;
  };
 
@@ -428,7 +426,6 @@ int target_arch_state(struct target_s *target);
 void target_handle_event( target_t *t, enum target_event e);
 void target_all_handle_event( enum target_event e );
 
-
 #define ERROR_TARGET_INVALID	(-300)
 #define ERROR_TARGET_INIT_FAILED (-301)
 #define ERROR_TARGET_TIMEOUT	(-302)
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 30447765..e98644b4 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -353,8 +353,6 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
 	fields[1].in_check_value = NULL;
 	fields[1].in_check_mask = NULL;
 
-
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = NULL;
@@ -474,8 +472,6 @@ int xscale_read_tx(target_t *target, int consume)
 	fields[1].in_check_value = NULL;
 	fields[1].in_check_mask = NULL;
 
-
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = NULL;
@@ -572,8 +568,6 @@ int xscale_write_rx(target_t *target)
 	fields[1].in_check_value = NULL;
 	fields[1].in_check_mask = NULL;
 
-
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
@@ -749,8 +743,6 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 	fields[1].in_check_value = NULL;
 	fields[1].in_check_mask = NULL;
 
-
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
@@ -1718,7 +1710,7 @@ int xscale_deassert_reset(target_t *target)
 
 			for (; buf_cnt < 32; buf_cnt += 4)
 			{
-					cache_line[buf_cnt / 4] = 0xe1a08008;
+				cache_line[buf_cnt / 4] = 0xe1a08008;
 			}
 
 			/* only load addresses other than the reset vectors */
@@ -1766,19 +1758,16 @@ int xscale_deassert_reset(target_t *target)
 		jtag_add_reset(0, 0);
 	}
 
-
 	return ERROR_OK;
 }
 
 int xscale_soft_reset_halt(struct target_s *target)
 {
-
 	return ERROR_OK;
 }
 
 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
 {
-
 	return ERROR_OK;
 }
 
@@ -2243,7 +2232,6 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	}
 
 	return ERROR_OK;
-
 }
 
 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
@@ -3041,7 +3029,6 @@ int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *targe
 
 int xscale_quit(void)
 {
-
 	return ERROR_OK;
 }
 
@@ -3267,7 +3254,6 @@ static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 	int domain;
 	u32 ap;
 
-
 	if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
 	{
 		return retval;
@@ -3295,7 +3281,6 @@ static int xscale_mmu(struct target_s *target, int *enabled)
 	return ERROR_OK;
 }
 
-
 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);